Flat panel display and method of manufacturing the same

1. A method of manufacturing a flat panel display, the method comprising:

forming a pixel unit on a substrate; and

forming a thin-film transistor (TFT) configured to drive the pixel unit,

wherein the forming of the TFT comprises:

forming a step difference layer having a relatively high step and a relatively low step on the substrate such that a top surface of the step difference layer has different heights measured from the substrate;

forming an amorphous silicon layer on the step difference layer along the top surface of the step difference layer;

crystallizing the amorphous silicon layer into a crystalline silicon layer; and

polishing the crystalline silicon layer to form a planarized surface of the crystalline silicon layer having no height differences so that the crystalline silicon layer, which remains on a region corresponding to the low step, becomes an active layer,

wherein the forming of the step difference layer comprises:

sequentially stacking a first insulating layer and a black matrix layer on the substrate;

removing at least a portion of the first insulating layer and at least a portion of the black matrix layer so as to form a step difference; and

forming a second insulating layer on the black matrix layer along the shape of the step difference.

2. A method of manufacturing a flat panel display, the method comprising:

forming a pixel unit on a substrate; and

forming a thin-film transistor (TFT) configured to drive the pixel unit,

wherein the forming of the TFT comprises:

forming a step difference layer having a relatively high step and a relatively low step on the substrate such that a top surface of the step difference layer has at least three different heights measured from the substrate, wherein the top surface is substantially parallel to the substrate;

forming an amorphous silicon layer on the step difference layer along the top surface of the step difference layer;

crystallizing the amorphous silicon layer into a crystalline silicon layer; and

polishing the crystalline silicon layer to form a planarized surface of the crystalline silicon layer having no height differences so that the crystalline silicon layer, which remains on a region corresponding to the low step, becomes an active layer.

3. The method of claim 2 , wherein the crystallizing of the amorphous silicon layer is performed by a sequential lateral solidification (SLS) method.

4. The method of claim 2 , wherein the polishing of the crystalline silicon layer is performed by a chemical mechanical polishing (CMP) process.

5. The method of claim 2 , wherein the forming of the TFT further comprises:

forming a gate electrode located substantially directly above the active layer; and

forming source/drain electrodes electrically connected to the active layer.

6. The method of claim 5 , wherein the forming of the pixel unit comprises:

forming a pixel electrode electrically connected to the source/drain electrodes;

forming a light-emitting layer on the pixel electrode; and

forming a facing electrode on the light-emitting layer to face the pixel electrode.

7. The method of claim 6 , wherein the light-emitting layer comprises one of an organic light-emitting layer and a liquid crystal layer.

8. The method of claim 2 , wherein the top surface of the step difference layer is continuous.