Lifetime mixed level non-volatile memory system
View Patent ↗A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
1. A system for storing data comprising:
at least one MLC non-volatile memory module comprising a plurality of individually erasable blocks;
at least one SLC non-volatile memory module comprising a plurality of individually erasable blocks; and
a controller coupled to the at least one MLC non-volatile memory module and the at least one SLC non-volatile memory module wherein the controller is adapted to:
a) maintain an address map of at least one of the MLC and SLC non-volatile memory modules, the address map comprising a list of logical address ranges accessible by a computer system, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory module or within the at least one MLC non-volatile memory module;
b) determine if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory module, fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the next available equivalent range of physical addresses within the at least one SLC non-volatile memory module;
c) determine which of the blocks of the plurality of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed; and
d) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory module.
2. The system of claim 1 , wherein the minimum quanta of addresses is equal to one block.
3. The system of claim 1 , wherein the minimum quanta of addresses is equal to one page.
4. The system of claim 1 , wherein the MLC non-volatile memory module is NAND flash memory.
5. The system of claim 1 , wherein the SLC non-volatile memory module is NAND flash memory.
6. The system of claim 1 , wherein the MLC non-volatile memory module is resistive random-access memory (RRAM).
7. The system of claim 1 , wherein the SLC non-volatile memory module is resistive random-access memory (RRAM).
8. The system of claim 1 , wherein the MLC non-volatile memory module is phase change memory (PCM).
9. The system of claim 1 , wherein the SLC non-volatile memory module is phase change memory (PCM).
10. The system of claim 1 , wherein the SLC non-volatile memory module is magnetic random-access memory (MAGRAM).
11. The system of claim 1 , wherein the controller causes the transfer of content on a periodic basis.