IP Library Patent Application 13455867
Patent Application
App. No. 13/455,867

MICROPROCESSOR TESTING CIRCUIT

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Patent No.
US None
App. No.
13/455,867
Abstract

A microprocessor testing circuit includes a sensor selection circuit to select a sensor measuring a characteristic of a microprocessor. An offset circuit artificially drives a signal from the selected sensor out of a predetermined range to invoke a fault operation in the microprocessor.

Claims (24)

1 . A microprocessor comprising:

a multiplexer having inputs connected to a plurality of sensors and connected to an external port via a switch, wherein each sensor outputs a voltage representative of measured characteristic of the microprocessor; and

an analog to digital converter (ADC) having an input connected to an output of the multiplexer, wherein the microprocessor determines whether a characteristic measured by one of the sensors is within a predetermined range based on signal values output from the ADC and an offset signal generated from an external system.

2 . The microprocessor of claim 1 , comprising a resistor connected between the switch and the output of the multiplexer wherein if the switch is closed, a voltage of the selected sensor output from the multiplexer is read via the resistor from the external port.

3 . The microprocessor of claim 2 , wherein the external system determines an offset amount for the offset signal based on the voltage read from the external port, and the offset amount when combined with the voltage read from the external port represents a measured characteristic outside the predetermined range.

4 . The microprocessor of claim 1 , comprising switch control logic to prevent the switch from being closed if the microprocessor is in a secure state.

5 . The microprocessor of claim 1 , wherein a voltmeter is to be connected to the external port if the switch is closed to read the voltages generated by each sensor as each of the inputs of the multiplexer are selected.

6 . A microprocessor testing circuit comprising:

a sensor selection circuit to select one of a plurality of sensors measuring characteristics of a microprocessor; and

an offset circuit to artificially drive a signal from a selected one of the plurality of sensors out of a predetermined range to invoke a fault operation in the microprocessor.

7 . The microprocessor testing circuit of claim 6 , wherein the sensor selection circuit comprises a multiplexer having inputs connected to the plurality of sensors and an input connected to an external port of the microprocessor via a switch, wherein each of the sensors outputs a voltage representative of measured characteristics of the microprocessor.

8 . The microprocessor testing circuit of claim 7 , wherein the offset circuit comprises the switch and a resistor, wherein the switch is connected between the external port and the resistor, and the resistor is connected to the switch and an output of the multiplexer.

9 . The microprocessor testing circuit of claim 8 , wherein an external system is connected to the offset circuit via the external port via the switch if the switch is closed, and the external system is to provide an offset signal to artificially drive the signal from the selected one of plurality of sensors out of the predetermined range.

10 . The microprocessor testing circuit of claim 9 , comprising an analog to digital converter (ADC) having an input connected to an output of the multiplexer, wherein the microprocessor determines whether the artificially driven signal is out of the predetermined range based on a signal value output from the ADC.

11 . The microprocessor testing circuit of claim 10 , wherein the microprocessor selects the input of the multiplexer connected to the external port to perform calibration using an external system providing varying voltages via the external port to the multiplexer and the ADC.

12 . The microprocessor testing circuit of claim 7 , wherein the plurality of sensors are calibrated by closing the switch and reading the voltages generated by the plurality of sensors via the external port by an external system as the multiplexer selects each of the sensors and as each sensor is tested throughout its range.

13 . A method of testing a microprocessor comprising:

determining whether testing and calibration is enabled in the microprocessor;

if the testing and calibration are enabled calibrating an analog to digital (ADC) converter or calibrating sensors measuring characteristics of a microprocessor; and

testing a security function of the microprocessor using the calibrations determined for the ADC or the sensors, wherein the testing comprises selecting one of the sensors through the multiplexer, converting an analog output of the selected sensor to a digital value through the ADC and the calibrations, determining an offset amount received from an external system, determining a combined value from the offset amount and the digital value, and detecting the combined value is out of a predetermined range for the selected sensor to invoke a fault operation.

14 . The method of claim 13 , comprising repeating the testing for each sensor.

15 . The method of claim 13 , comprising:

determining whether the microprocessor is not in a secure state; and

if the microprocessor is not in the secure state, enabling the external system to read the output of the selected sensor.

Assignments (11)
RELEASE OF SECURITY INTEREST REEL/FRAME 044183/0577 Recorded Feb 2, 2023
From: JPMORGAN CHASE BANK, N.A.
To: MICRO FOCUS LLC (F/K/A ENTIT SOFTWARE LLC)
Reel/Frame 063560/0001 →
RELEASE OF SECURITY INTEREST REEL/FRAME 044183/0718 Recorded Feb 2, 2023
From: JPMORGAN CHASE BANK, N.A.
To: MICRO FOCUS LLC (F/K/A ENTIT SOFTWARE LLC); BORLAND SOFTWARE CORPORATION; MICRO FOCUS (US), INC.; SERENA SOFTWARE, INC; ATTACHMATE CORPORATION; MICRO FOCUS SOFTWARE INC. (F/K/A NOVELL, INC.); NETIQ CORPORATION
Reel/Frame 062746/0399 →
RELEASE OF SECURITY INTEREST Recorded Aug 22, 2019
From: NIBC BANK N.V., AS SECURITY AGENT
To: UTIMACO INC.
Reel/Frame 050135/0404 →
SECURITY INTEREST Recorded Feb 5, 2019
From: UTIMACO INC.
To: NIBC BANK N.V.
Reel/Frame 048240/0281 →
RELEASE OF SECURITY INTEREST Recorded Oct 24, 2018
From: JPMORGAN CHASE BANK, N.A. (AS SUCCESSOR TO BANK OF AMERICA, N.A.)
To: ENTIT SOFTWARE LLC
Reel/Frame 047297/0843 →
RELEASE OF SECURITY INTEREST Recorded Oct 24, 2018
From: JPMORGAN CHASE BANK, N.A. (AS SUCCESSOR TO BANK OF AMERICA, N.A.)
To: ENTIT SOFTWARE LLC
Reel/Frame 047299/0055 →
SECURITY INTEREST Recorded Oct 11, 2017
From: ATTACHMATE CORPORATION; BORLAND SOFTWARE CORPORATION; NETIQ CORPORATION; MICRO FOCUS (US), INC.; MICRO FOCUS SOFTWARE, INC.; ENTIT SOFTWARE LLC; ARCSIGHT, LLC; SERENA SOFTWARE, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 044183/0718 →
SECURITY INTEREST Recorded Oct 11, 2017
From: ENTIT SOFTWARE LLC; ARCSIGHT, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 044183/0577 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2017
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
To: ENTIT SOFTWARE LLC
Reel/Frame 042746/0130 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2012
From: HADLEY, TED A.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 028111/0925 →