IP Library Granted Patent US 9,087,029
Granted Patent B2
US 9,087,029 · App. 13/457,045 · Granted Jul 21, 2015

Qualifying circuit board materials

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,087,029
App. No.
13/457,045
Granted
Jul 21, 2015
Kind
B2
Abstract

A test structure for testing electrical properties of a material comprises a first loop and a second loop, which are connected to form a closed test loop. A signal generator, for generating a test signal, is coupled to the first loop and the second loop. A signal propagation switching logic is coupled to the first loop and to the second loop for alternatingly flipping the test signal between the first and second loops, such that the test signal moves uninterrupted through the closed test loop. A probe logic detects any degradation of the test signal as the test signal travels along the closed test loop.

Claims (42)

1. A system comprising:

a processor; and

a test structure coupled to the processor, wherein the test structure comprises:

a first loop having a first end and a second end;

a second loop having a third end and a fourth end;

a closed test loop made up of the second end connected to the third end and the first end connected to the fourth end;

a signal generator coupled to the first loop and the second loop, wherein the signal generator generates a signal;

a signal propagation switching logic coupled to the first loop and to the second loop, wherein the signal propagation switching logic alternatingly flips the signal between the first and second loops to permit the signal to move uninterrupted through the closed test loop; and

a probe logic for detecting a degradation of the signal as the signal travels along the closed test loop.

2. The system of claim 1 , wherein the signal is a voltage, wherein the first and second loops are electrical conductors that are separated by an insulation material, and wherein the degradation is caused by a voltage leakage into the insulation material.

3. The system of claim 2 , wherein the insulation material is a dielectric insulator used to fabricate printed circuit boards.

4. The system of claim 1 , wherein the test structure further comprises:

a first diode in the first loop; and

a second diode in the second loop, wherein the first and second diodes are oriented to keep the signal traveling in a same direction through the closed test loop.

5. The system of claim 1 , wherein the test structure comprises more than two loops that are connected to form the closed test loop.

6. A system comprising:

a processor; and

a test structure coupled to the processor, wherein the test structure comprises:

a first loop of conducting material, wherein the first loop has a first end and a second end;

a second loop of the conducting material, wherein the second loop has a third end and a fourth end;

a closed test loop made up of the second end connected to the third end and the first end connected to the fourth end;

a signal generator coupled to the first loop and the second loop, wherein the signal generator generates a signal;

a signal propagation switching logic coupled to the first loop and to the second loop, wherein the signal propagation switching logic alternatingly flips the signal between the first and second loops to permit the signal to move uninterrupted through

the closed test loop; and

a probe logic for detecting a degraded test signal that is caused by a degradation of the signal as the signal travels along the closed test loop, wherein

the signal propagation switching logic flips the degraded test signal to the third end of the second loop while flipping the fourth end of the second loop to zero, and wherein the signal propagation switching logic repeatedly flips the degraded test signal between the first loop and the second loop to create a further degraded test signal.

7. The system of claim 6 , wherein the signal is a voltage, wherein the first and second loops are electrical conductors that are separated by an insulation material, and wherein the degradation is caused by a voltage leakage into the insulation material.

8. The system of claim 7 , wherein the insulation material is a dielectric insulator used to fabricate printed circuit boards.

9. The system of claim 6 , wherein the test structure further comprises:

a first diode in the first loop; and

a second diode in the second loop, wherein the first and second diodes are oriented to keep the signal traveling in a same direction through the closed test loop.

10. The system of claim 6 , wherein the test structure comprises more than two loops that are connected to form the closed test loop.

11. The system of claim 6 , further comprising:

a display for displaying the degraded and further degraded test signals.

12. A test structure comprising:

a first loop of conducting material, wherein the first loop has a first end and a second end;

a second loop of the conducting material, wherein the second loop has a third end and a fourth end;

a closed test loop of the conducting material made up of the second end connected to the third end and the first end connected to the fourth end, wherein the first loop and the second are separated by an insulation material;

a signal generator coupled to the first loop and the second loop, wherein the signal generator generates a test signal;

a signal propagation switching logic coupled to the first loop and to the second loop, wherein the signal propagation switching logic alternatingly flips the test signal between the first and second loops to permit the test signal to move uninterrupted through the closed test loop; and

a probe logic for detecting a degradation of the test signal as the test signal travels along the closed test loop, wherein the signal generator initiates the test signal at the first end of the first loop, wherein the probe logic detects a degraded test signal at the second end of the first loop, wherein the signal propagation switching logic flips the degraded test signal to the third end of the second loop while flipping the fourth end of the second loop to zero, wherein the probe logic detects a further degraded test signal at the fourth end of the second loop, wherein the signal propagation switching logic flips the further degraded test signal to the first end of the first loop while flipping the second end of the first loop to zero, and wherein the detecting and flipping is repeated until a testing cycle is completed, wherein the degraded and further degraded test signals result from signal leakage from the conducting material into the insulating material.

13. The test structure of claim 12 , wherein the test signal is a voltage, and wherein the degraded and further degraded test signals are a voltage drop of the test signal as the test signal travels through the closed test loop.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2019
From: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE LTD.
To: LENOVO INTERNATIONAL LIMITED
Reel/Frame 050300/0878 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENT CONTAINING TYPO ERRORS PREVIOUSLY RECORDED AT REEL: 037101 FRAME: 0969. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 28, 2015
From: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
To: LENOVO INTERNATIONAL LIMITED
Reel/Frame 037689/0190 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2015
From: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
To: LENOVO INTERNATIONAL LIMITED
Reel/Frame 037101/0969 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
Reel/Frame 034194/0111 →