Nonvolatile memory systems with embedded fast read and write memories
View Patent ↗A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
1. A memory system comprising:
a non-volatile memory organized to include a plurality of blocks each having a plurality of pages;
a volatile memory;
a first buffer capable of temporarily storing at least one page;
a second buffer configured to receive information associated with one or more write requests, said write requests being associated with one or more changes to one or more portions of a page in said non-volatile memory, said one or more portions being less than the entirety of said page;
said system adapted to locate said page associated with said one or more write requests in said non-volatile memory, and to selectively write said page to said first buffer;
said system further adapted to locate in said first buffer said one or more portions of said page associated with said one or more write requests, and to selectively write said one or more portions to said volatile memory without writing the entirety of said page in said first buffer to said volatile memory;
said system further adapted to write said one or more changes from said second buffer to said volatile memory, thereby updating said one or more updated portions from said volatile memory to said first buffer, thereby updating said page stored therein to include said one or more changes associated with said one or more write request; and
said system further adapted to write said updated page from said first buffer to an erased page in said non-volatile memory.
2. A memory system as defined in claim 1 wherein said non-volatile memory comprises a NAND flash memory.
3. A memory system as defined in claim 1 wherein said volatile memory comprises a dynamic random access memory (DRAM).
4. A flash memory system comprising:
a NAND flash memory organized to include a plurality of blocks each having a a plurality of pages;
a volatile memory;
a controller;
a first buffer capable of temporarily storing at least one page;
a second buffer configured to receive information associated with one or more write requests, said write requests being associated with one or more changes to one or more portions of a page in said NAND flash memory, said one or more portions being less than the entirety of said page;
said controller locating said page associated with said one or more write requests in said NAND flash memory, and selectively writing said page from said NAND flash memory to said first buffer;
said controller further locating in said first buffer said one or more portions of said page associated with said one or more write requests, and selectively writing said one or more portions to said volatile memory without writing the entirety of said page in said first buffer to said volatile memory;
said controller further writing said one or more changes from said second buffer to said volatile memory, thereby updating said one or more portions associated with said one or more write requests to include said one or more changes; and
said controller further writing said one or more updated portions from said volatile memory to said first buffer, thereby updating said page stored therein to include said one or more changes associated with said one or more write requests; and
said controller further writing said updated page from said first buffer to an erased page in said NAND flash memory.
5. A flash memory system as defined in claim 4 wherein said volatile memory comprises a dynamic random access memory (DRAM).
6. In a memory system which includes a non-volatile memory organized to include a plurality of blocks each having a plurality of pages, a volatile memory, a first buffer capable of temporarily storing at least one page, and a second buffer configured to receive information associated with one or more write requests, said write requests being associated with one or more changes to one or more portions of a page in said non-volatile memory, said one or more portions being less than the entirety of said page, the method for writing said one or more changes requested by said one or more write request to one or more portions of a page in said non-volatile memory, comprising the steps of:
receiving in said second buffer information associated with said one or more write requests;
locating in said non-volatile memory said page associated with said one or more write requests;
selectively writing said located page to said first buffer;
locating in said first buffer said one or more portions of said page associated with said one or more write requests;
selectively writing said one or more portions of said volatile memory without writing the entirety of said page in said first buffer to said volatile memory;
writing said one or more changes from said second buffer to said volatile memory, thereby updating said one or more portions associated with said one or more write requests to include said one or more changes;
writing said one or more updated portions from said volatile memory to said first buffer, thereby updating said pages stored therein to include said one or more changes associated with said one or more write requests; and
writing said updated page from said first buffer to an erased page in said non-volatile memory.
7. The method defined in claim 6 including the additional step of providing a NAND flash as said non-volatile memory.
8. The method defined in claim 6 including the additional step of providing a dynamic random access memory (DRAM) as said volatile memory.
9. The memory system as defined in claim 1 or 4 wherein said non-volatile memory is a magnetic RAM.
10. The memory system as defined in claim 1 or 4 wherein said non-volatile memory is a resistive RAM.
11. The memory system as defined in claim 1 or 4 wherein said non-volatile memory is a ferroelectric memory.
12. The memory system as defined in claim 1 or 4 wherein said non-volatile memory is a nanotube memory.
13. The memory system as defined in claim 1 or 4 wherein said non-volatile memory is a phase change memory.
14. The memory system as defined in claim 1 or 4 , wherein said volatile memory comprises a static random access memory (SRAM).
15. The memory system as defined in claim 1 or 4 wherein said first buffer comprises a static random access memory (SRAM).
16. The method in claim 6 including the additional step of providing a static random access memory (SRAM) as said volatile memory.
17. The method defined in claimed 6 including the additional step of providing a static random access memory (SRAM) as said first buffer.