Reconfigurable integrated circuit device

1. A reconfigurable integrated circuit device, which is configured by configuration data comprising:

a plurality of processing elements each of which includes an arithmetic circuit, and which are configured by the configuration data; and

an inter-processing element network which connects the plurality of processing elements in a state configured by the configuration data, wherein

the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, the processing element includes an input data holding register which holds the input data signal, an arithmetic processing circuit which computes the input data signal, and an output data holding register which holds computing result data of the arithmetic processing circuit,

when updating from a first context which includes a circuit configured by a first configuration data to a second context which follows the first context and includes a circuit configured by a second configuration data, a second processing element which is included in the second context and is configured in a hold mode holds, in the input data holding register, as the input data signal, an output data signal held by an output data holding register of a first processing element which is included in the first context,

when the configuration of the processing element is updated by configuration data that makes the hold mode valid, the processing element inputs the input data signal held in the input data holding register to the arithmetic processing circuit, and

when the configuration of the processing element is updated by configuration data that makes the hold mode invalid, the processing element continuously inputs the input data signal, which is to be input, to the arithmetic processing circuit without using the input data holding register.

2. The reconfigurable integrated circuit device according to claim 1 , wherein

the processing element inputs the configuration data in response to a fetch enable signal to update the configuration, and

the processing element makes the output valid signal invalid, and disables latching of an output data signal by the output data holding register upon the update, in response to the fetch enable signal, regardless whether the mode is the hold mode or not.

3. The reconfigurable integrated circuit device according to claim 1 , wherein

upon update to the second context, a first output data signal held by the output data holding register of the first processing element is input by the second processing element, so that the arithmetic processing circuit starts computing processing, and the first output data signal upon the update is held in the input data holding register as an input data signal, and the input data signal held in the input data holding register is input in the arithmetic processing circuit.

4. A reconfigurable integrated circuit device, which is configured by configuration data comprising:

a plurality of processing elements each of which includes an arithmetic circuit, and which are configured by the configuration data; and

an inter-processing element network which connects the plurality of processing elements in a state configured by the configuration data, wherein

the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, the processing element includes an input data holding register which holds the input data signal, an arithmetic processing circuit which computes the input data signal, and an output data holding register which holds computing result data of the arithmetic processing circuit,

when updating from a first context which includes a circuit configured by a first configuration data to a second context which follows the first context and includes a circuit configured by a second configuration data, a second processing element which is included in the second context and is configured in a hold mode holds, in the input data holding register, as the input data signal, an output data signal held by an output data holding register of a first processing element which is included in the first context, and

in the second context, an output terminal of the first processing element is connected to an input terminal of the second processing element, and is also connected to an input terminal of a third processing element configured by configuration data which makes the hold mode invalid.

5. A reconfigurable integrated circuit device, which is configured by configuration data, comprising:

a plurality of processing elements each of which includes an arithmetic circuit and which are configured by the configuration data; and

an inter-processing element network which connects the plurality of processing elements in a state configured by the configuration data, wherein

the processing element inputs an input valid signal and an input data signal, outputs an output valid signal and an output data signal, the processing element includes an arithmetic processing circuit which computes the input data signal, an output data holding register which holds the computing result data of the arithmetic processing circuit, and an output valid signal generation circuit which generates the output valid signal, and

in the processing element,

when a configuration of the processing element is updated by configuration data which makes the hold mode valid, the arithmetic processing circuit computes the input data signal while the input valid signal is invalid upon the update, and the output valid signal generation circuit outputs the output valid signal in response to a hold mode signal in synchronization with the output of the output data signal corresponding to the input data signal upon the update and

when a configuration of the processing element is updated by configuration data which makes the hold mode invalid, the output valid signal generation circuit outputs the output valid signal in response to a valid input valid signal in synchronization with the output of the output data signal corresponding to the input data when the valid input valid signal is received.

6. The reconfigurable integrated circuit device according to claim 5 , wherein

the processing element further includes an input data holding register,

in the processing element,

when the configuration is updated by configuration data which makes the hold mode valid, an input data signal upon the update is held by the input data holding register and is output to the arithmetic processing circuit, and

when the configuration is updated by configuration data which makes the hold mode invalid, the arithmetic processing circuit inputs an input data signal which is input after the update and performs computing processing, without using the input data holding register.

7. The reconfigurable integrated circuit device according to claim 5 , wherein

between a first context which includes a circuit configured by a first configuration data and a second context which follows the first context and includes a circuit configured by a second configuration data, upon update to the second context, an output data signal held by an output data holding register of a first processing element included in the first context is input by a second processing element which is included in the second context and is configured in the hold mode and computed by the arithmetic processing circuit.

8. The reconfigurable integrated circuit device according to claim 6 , wherein

between a first context which includes a circuit configured by a first configuration data and a second context which follows the first context and includes a circuit configured by a second configuration data, upon update to the second context, a first output data signal held by an output data holding register of a first processing element included in the first context is input by a second processing element which is included in the second context and is reconfigured in the hold mode then the arithmetic processing circuit starts computing processing, and the first output data signal upon the update is held in the input data holding register as an input data signal, and the input data signal held in the input data holding register is input in the arithmetic processing circuit.

9. A reconfigurable integrated circuit device, which is configured by configuration data, comprising:

a plurality of processing elements each of which includes an arithmetic circuit, and which are configured by the configuration data; and

an inter-processing element network which connects the plurality of processing elements in a state configured by the configuration data, wherein

the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, the processing element includes an input data holding register which holds the input data signal, an arithmetic processing circuit which computes the input data signal, and an output data holding register which holds the computing result data of the arithmetic processing circuit, and

when a configuration of the processing element is updated by configuration data which makes a hold mode valid, the input data holding register holds the input data signal upon the update in response to a hold mode signal immediately after the update, the arithmetic processing circuit performs computing processing on the input data signal which is held in the input data holding register, and

the processing element outputs the output valid signal in synchronization with the output of the output data signal corresponding to the computing result data in response to the hold mode signal even if the input valid signal is invalid.

10. The reconfigurable integrated circuit device according to claim 1 , wherein

when the configuration of the processor element is updated by configuration data that makes the hold mode valid, the processor element inputs an input data signal which is input upon the update to the arithmetic processing circuit without using the input data holding register, and then inputs the input data signal held in the input data holding register to the arithmetic processing circuit.