Semiconductor device and method of forming the same
A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.
1. A semiconductor device comprising:
a semiconductor substrate having a first gate groove;
a first fin structure underneath a top of the first gate groove;
a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove;
a second diffusion region in the semiconductor substrate, the second diffusion region covering a second side of the first gate groove, the second diffusion region having a bottom which is deeper than a top of the first fin structure; and
a channel region extending between the first and second diffusion regions through the surface of the first fin structure and along the first side of the first gate groove, without the channel region extending along the second side of the first gate groove.
2. The semiconductor device according to claim 1 , wherein the bottom of the second diffusion region is shallower than a bottom of the first fin structure.
3. The semiconductor device according to claim 1 , wherein the first gate groove has a bottom that has a depth from a surface of the semiconductor substrate in the range from 150 nm to 200 nm, and the first fin structure has a height in the range from 10 nm to 40 nm.
4. The semiconductor device according to claim 1 , further comprising:
a first gate insulating film that covers the first gate groove and a surface of the first fin structure; and
a first gate electrode on the first gate insulating film in a lower portion of the first gate groove, the first gate electrode extending over the first fin structure.
5. The semiconductor device according to claim 2 , wherein the semiconductor substrate has a second gate groove having a second side of the second gate groove that is covered by the second diffusion region.
6. The semiconductor device according to claim 5 , further comprising:
a second fin structure underneath a top of the second gate groove; and
a third diffusion region in the semiconductor substrate, the third diffusion region covering an upper portion of a first side of the second gate groove,
wherein the second diffusion region has a bottom which is deeper than a top of the second fin structure and shallower than a bottom of the second fin structure.
7. The semiconductor device according to claim 6 , wherein the second gate groove has a bottom that has a depth from a surface of the semiconductor substrate in the range from 150 nm to 200 nm, and the second fin structure has a height in the range from 10 nm to 40 nm.
8. The semiconductor device according to claim 6 , further comprising:
a second gate insulating film that covers the second gate groove and a surface of the second fin structure; and
a second gate electrode on the second gate insulating film in a lower portion of the second gate groove, the second gate electrode extending over the second fin structure.
9. The semiconductor device according to claim 4 , wherein the first diffusion region has a bottom that is shallower by a range of 5 nm to 10 nm than a top surface of the first gate electrode.
10. The semiconductor device according to claim 1 , wherein the first fin structure has a top ridge and first and second side surfaces opposing to each other, and the top ridge extends across the first gate groove from the first side of the first gate groove to the second side of the first gate groove, and the first and second side surfaces extend in parallel to a first direction in which the top ridge extends.
11. The semiconductor device according to claim 10 , further comprising:
a plurality of first isolation regions in the semiconductor device, the plurality of first isolation regions defining active regions, the plurality of first isolation regions extending in the first direction,
wherein the gate groove extends in a second direction and across the active region and the first isolation region.
12. The semiconductor device according to claim 11 , further comprising:
a plurality of second isolation regions extending in the second direction and in the semiconductor device, the plurality of second isolation regions defining device regions in each of the active regions.
13. The semiconductor device according to claim 1 , further comprising:
a bit line electrically coupled to the second diffusion region, and the bit line extending across the gate groove.
14. The semiconductor device according to claim 1 , further comprising:
a capacitor electrically coupled to the first diffusion region.
15. The semiconductor device according to claim 4 , wherein the first gate insulating film has an equivalent oxide thickness in the range of 4 nm to 6 nm, and the first gate electrode has a work function in the range from 4.6 eV to 4.8 eV, and the first gate electrode has a threshold voltage in the range from 0.8 V to 1.0 V.
16. A semiconductor device comprising:
a semiconductor substrate having a first gate groove;
a first fin structure underneath a top of the first gate groove;
a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove;
a second diffusion region in the semiconductor substrate, the second diffusion region covering a second side of the first gate groove; and
a channel region extending between the first and second diffusion regions through the surface of the fin structure and along the first side of the first gate groove, without the channel region extending along the second side of the first gate groove.
17. The semiconductor device according to claim 16 , wherein the first gate groove has a bottom that has a depth from a surface of the semiconductor substrate in the range from 150 nm to 200 nm, and the first fin structure has a height in the range from 10 nm to 40 nm.
18. A semiconductor device comprising:
a semiconductor substrate having a first gate groove;
a first fin structure underneath a top of the first gate groove;
a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and
a second diffusion region in the semiconductor substrate, the second diffusion region covering a second side of the first gate groove,
wherein the first gate groove has a bottom that has a depth from a surface of the semiconductor substrate in the range from 150 nm to 200 nm, and the first fin structure has a height in the range from 10 nm to 40 nm.