Method to configure serial communications and device thereof
View Patent ↗In response to a reset condition, the state of a steady-state signal at an I/O pin of the serial communication port of an integrated circuit die is determined. The serial communication port is configured to support one of the plurality of serial communication protocols based upon the detected steady-state condition.
1. A method comprising:
detecting an initial steady-state signal at an I/O pin of an integrated circuit die subsequent to a reset condition; and,
configuring, in response to the initial steady-state signal having a first steady state, a set of pins of the integrated circuit, including the I/O pin, as a first serial communication port that implements a first serial communication protocol, otherwise, in response to the initial steady-state signal having second steady state, configuring a second serial communication port at the integrated circuit that implements a second serial communication protocol, wherein the second serial communication port includes at least a portion of the set of pins.
2. The method of claim 1 , wherein the first serial communication protocol defines a Serial Peripheral Interface (SPI) bus.
3. The method of claim 2 , wherein the second serial communication protocol defines an (Inter IC) I2C bus.
4. The method of claim 1 , wherein the second serial communications protocol defines an (Inter IC) I2C bus.
5. The method of claim 4 , wherein the first I/O pin defines a logic state of an I2C slave address of the integrated circuit die.
6. The method of claim 1 , wherein in response to the initial steady-state signal having the first steady state further indicates that a predetermined bit of an I2C slave address of the integrated circuit die is a first binary logic state.
7. The method of claim 1 , wherein one of the first steady state and the second steady state is a HI-Z state, and determining the first I/O pin is being driven to the HI-Z steady state comprises detecting a midpoint voltage of a voltage divider of the integrated circuit die.
8. The method of claim 1 , wherein one of the first steady state and the second steady state is a HI-Z steady state, and determining the first I/O pin is being driven to the HI-Z steady state comprises detecting a rise/fall time.
9. The method of claim 1 , wherein the first steady state is a high-voltage logic state or a low-voltage logic state, and the second steady-state is a HI-Z steady state.
10. A device comprising:
a first serial interface module to implement a first serial communication protocol at a first set of I/O pins of an integrated circuit device, the first set of I/O pins including a first I/O pin and a second I/O pin;
a second serial interface module to implement a second serial communication protocol at a subset of the first set of I/O pins wherein the subset includes the first pin;
a state detect module to determine an initial steady-state signal at the first I/O pin of an integrated circuit device subsequent to a reset condition; and
a select module to enable the first interface module in response to the state detect module detecting a first steady state at the first I/O pin, otherwise the select module to enable the second interface module in response to the state detect module detecting a second steady state at the I/O first pin.
11. The device of claim 10 , wherein the first serial communication protocol is the Serial Peripheral (SPI) protocol and the second serial communication protocol is the I2C protocol.
12. The device of claim 10 , wherein the first steady state is a HI-Z state.
13. The device of claim 10 , wherein the device is an integrated circuit die comprising an I/O peripheral region surrounding a logic core region, and the select module substantially resides in at the I/O peripheral region.
14. The device of claim 13 , wherein the first and second interface modules substantially reside at the logic core region.
15. The device of claim 10 , wherein the state detect module comprises a window comparator.
16. The device of claim 15 wherein the window comparator comprises:
a first comparator comprising a first input, a second input, and first output coupled to the select module to provide a select signal to enable one of the first interface module and the second interface module;
a second comparator comprising a third input, a fourth input, and a second output;
a first voltage divider comprising a first node coupled to provide a first voltage to the first I/O pin, to the first input of the first comparator, and to the third input of the second comparator; and
a second voltage divider comprising a first node coupled to the second input of the first comparator, and a second node coupled to the fourth input of the second comparator.
17. The device of claim 10 , wherein the state detect module comprises a current detector.
18. The device of claim 10 , wherein the state detect module comprises a rise time detector.
19. A method comprising:
determining at an integrated circuit whether, subsequent to a reset condition, a first input/output (I/O) pin of an integrated circuit is initially being driven to a first steady state, a second steady state, or a third steady state; and
in response to determining that the first I/O pin is being driven to either the first steady state or to the second steady state, configuring a set of I/O pins of the integrated circuit, that includes the first I/O pin, as a first serial bus interface that implements a first serial communication protocol, otherwise, in response to determining that the first I/O pin is being driven to the third steady state, configuring at least a portion of the set of I/O pins as a second serial bus interface that implements a second serial communication protocol.
20. The method of claim 19 , wherein the first steady state is a logic zero state, the second steady state is a logic one state, and the third steady state is a HI-Z state.