Receiver having limiter-enhanced data eye openings
View Patent ↗A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.
1. A receiver having an input and adapted to receive a signal from a communication channel, comprising:
an equalizer, coupled to the input of the receiver, having an output;
a limiter, coupled to the output of the equalizer, having an output, wherein the limiter is a saturable amplifier;
a variable delay circuit, coupled to the output of the equalizer, having an output;
a decision circuit, coupled to the output of the limiter, having an output and a clock input; and
a clock recovery circuit, coupled to the output of the variable delay circuit and not connected to the output of the limiter, for generating a clock signal coupled to the clock input of the decision circuit.
2. The receiver of claim 1 further comprising:
an adaption circuit, coupled to the output of the decision circuit and the output of the equalizer;
wherein the equalizer is an adaptive equalizer having coefficient values controlled by the adaptation circuit and the decision circuit has at least one threshold value controlled by the adaptation circuit.
3. The receiver of claim 2 wherein the adaptation circuit comprises:
an error detection circuit, coupled to the output of the decision circuit and the output of the adaptive equalizer, for producing an error signal; and
an adaptation controller, coupled to the output of the error detector circuit and the output of the decision circuit, is adapted to implement an adaptation algorithm for reducing the error signal by controlling the coefficients of the adaptive equalizer.
4. The receiver of claim 3 wherein the adaptive equalizer comprises a decision feedback equalizer having multiple tap coefficients controlled by the adaptation controller, the at least one threshold value being substantially equal to one of the tap coefficients.
5. The receiver of claim 3 wherein the adaptation algorithm is a least-mean-square algorithm for reducing a mean-square of the error signal.
6. The receiver of claim 3 further comprising a back channel for communicating transmit filter coefficient values generated by the adaptation controller to a transmitter coupled to the communications channel.
7. The receiver of claim 1 wherein the signal is a baseband digital signal and the communication channel is a backplane.
8. The receiver of claim 1
wherein the clock recovery circuit is coupled to the output of the variable delay circuit, the limiter has a propagation delay, and the variable delay circuit provides a delay for at least partially compensating for the propagation delay of the limiter.
9. The receiver of claim 8 further comprising:
an error detection circuit, coupled to the output of the decision circuit and the output of the variable delay circuit, having an output; and
an adaption controller, coupled to the output of the decision circuit and the output of the error detection circuit;
wherein the equalizer is a multi-tap adaptive equalizer having tap coefficient values controlled by the adaptation controller.
10. A receiver having an input and adapted to receive a signal from a communication channel, comprising:
an analog front end, coupled to the input of the receiver, having an output and at least one filter coefficient;
an adaptive equalizer, coupled to the output of the analog front end, having an output and tap coefficient values;
a limiter, coupled to the output of the equalizer, having an output;
a decision circuit, coupled to the output of the limiter, having an output and a clock input and at least one threshold value;
a variable delay circuit, coupled to the output of the equalizer, having an output;
an error detection circuit, coupled to the output of the decision circuit and the output of the variable delay circuit, for producing an error signal;
an adaption controller, coupled to the output of the decision circuit and responsive to the error signal, adapted to implement a least-mean-squared algorithm for reducing the error signal by controlling the tap coefficient values of the adaptive equalizer, the at least one threshold value of the decision circuit, and the at least one filter coefficient of the analog front end; and
a clock recovery circuit, coupled to the output of the equalizer and not connected to the output of the limiter, for generating a clock signal coupled to the clock input of the decision circuit;
wherein the clock recovery circuit is coupled to the output of the variable delay circuit, the limiter has a propagation delay, the variable delay circuit provides a delay for at least partially compensating for the propagation delay, and the threshold value is set to approximately an average value of an output signal on the output of the limiter.
11. The receiver of claim 10 further comprising a back channel for communicating transmit filter coefficient values generated by the adaptation controller to a transmitter coupled to the communications channel;
wherein the signal is a baseband digital signal and the communication channel is a backplane, and the at least one threshold value is proportional to a residual post-cursor tap coefficient value of the adaptive equalizer.
12. The receiver of claim 11 wherein the limiter is a saturable amplifier.