Virtualized instruction extensions for system partitioning
View Patent ↗A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61 ) by executing a control instruction ( 47, 48 ) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register ( 25 ) at a physical address (PA) retrieved from a special purpose register ( 46 ) so that the partitioned device ( 14, 61 ) can determine if the access command can be performed based on local access control information.
1. A non-transitory computer readable storage medium comprising a first device control instruction of an instruction set architecture, which when executed on a processor, causes the processor to access a partitioned interrupt controller by:
generating an access command for the partitioned interrupt controller;
retrieving a partition parameter for the access command from a first hardware register;
generating a storage address for a predetermined storage location at the partitioned interrupt controller;
encoding the access command and partition parameter into a data payload; and
writing the data payload to the predetermined storage location at the partitioned interrupt controller using the storage address.
2. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to generate the access command by generating an end-of-instruction (EOI) command to the interrupt controller to take an identified interrupt request out of service to an idle state.
3. The computer readable storage medium of claim 1 , where write access to the first hardware register is restricted to trusted higher-level software.
4. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to generate the storage address by retrieving the storage address from a second hardware register.
5. The computer readable storage medium of claim 4 , where write access to the second hardware register is restricted to trusted higher-level software.
6. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to generate the storage address by accessing a device table with a device identifier for the partitioned interrupt controller to retrieve the storage address.
7. The computer readable storage medium of claim 6 , where write access to the device table is restricted to trusted higher-level software.
8. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to write the data payload to a command register at the partitioned interrupt controller using the storage address.
9. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to write the data payload to the predetermined storage location using a memory-mapped secure store operation.
10. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to encode the data payload by setting a predetermined bit in the data payload to a first value indicate that the access command is generated by trusted higher-level software.
11. The computer readable storage medium of claim 1 , where the first device control instruction causes the processor to encode the data payload by setting a predetermined bit in the data payload to a second value indicate that the access command is generated by guest supervisor.
12. A method of managing a resource in a partitioned computer system, comprising:
generating a command for the resource;
retrieving a partition parameter from a first hardware register;
generating a storage address for a predetermined storage location at the resource;
encoding the command and the partition identifier into a data payload for storage to the predetermined storage location at the resource using the storage address; and
writing the data payload to the predetermined storage location using a memory-mapped secure store operation.
13. The method of claim 12 , where the resource comprises an interrupt controller which receives and prioritizes partitioned interrupt requests from one or more interrupt sources to deliver a top priority interrupt to a processor.
14. The method of claim 12 , where generating the storage address comprises retrieving the storage address from a dedicated address register.
15. The method of claim 14 , where write access to either or both of the dedicated address register and the first hardware register is restricted to trusted higher-level software.
16. The method of claim 12 , where the partitioned computer system comprises a processor and a partitioned resource, said processor executing a resource control instruction to perform a secure store operation of the data payload to the storage address at the partitioned resource comprising the command and a logical partition identifier (LPID), and said partitioned resource using the logical partition identifier (LPID) as a qualifier to determine if the command can be performed based on local access control information.
17. The method of claim 16 , where the dedicated storage address and logical partition identifier (LPID) are managed by trusted software.
18. A data processing system comprising:
a partitioned interrupt controller; and
a processor coupled to the partitioned interrupt controller, wherein the processor executes an interrupt control instruction to encode a data payload with a command and a logical partition identifier (LPID) associated with a first interrupt request, and to perform a secure store operation of the data payload to a storage address at the partitioned resource using a memory-mapped secure store operation, where the storage address is retrieved from a dedicated address register at the processor.