Chip blanking and processing in SCDMA to mitigate impulse and burst noise and/or distortion
View Patent ↗A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication.
1. An apparatus, comprising:
an input to receive a first plurality of forward error correction (FEC) encoded signals; and
a decoder to:
process the first plurality of FEC encoded signals to generate a plurality of hard decisions;
remodulate the plurality of hard decisions to generate a plurality of remodulated signals;
based on comparison of the first plurality of FEC encoded signals and the plurality of remodulated signals, selectively mark at least one portion of the first plurality of FEC encoded signals as at least one erasure to generate a second plurality of FEC encoded signals; and
decode the second plurality of FEC encoded signals to make at least one estimate of at least one information encoded therein.
2. The apparatus of claim 1 , wherein:
the plurality of FEC encoded signals includes a first interleaved Reed-Solomon (RS) encoded signal including a plurality of codewords;
second plurality of FEC encoded signals includes a second interleaved RS encoded signal; and
based on at least one error location within a first of the plurality of codewords, the decoder selectively to mark at least one portion of at least a second of the plurality of codewords to generate the second interleaved RS encoded signal.
3. The apparatus of claim 1 , wherein:
the decoder to:
perform partial decoding of the first plurality of FEC encoded signals to identify at least one error location therein;
based on the at least one error location and based on comparison of the first plurality of FEC encoded signals and the plurality of remodulated signals, selectively mark the at least one portion of the first plurality of FEC encoded signals as the at least one erasure to generate the second plurality of FEC encoded signals; and
decode the second plurality of FEC encoded signals to make the at least one estimate of the at least one information encoded therein.
4. The apparatus of claim 1 , wherein:
the at least one portion of the first plurality of FEC encoded signals is a symbol or a bit of at least one of the first plurality of FEC encoded signals.
5. The apparatus of claim 1 , wherein:
the input to receive the first plurality of FEC encoded signals at or during a first time;
the input to receive a third plurality of FEC encoded signals at or during a second time; and
the decoder to:
process the third plurality of FEC encoded signals to generate at least one additional plurality of hard decisions;
remodulate the at least one additional plurality of hard decisions to generate at least one additional plurality of remodulated signals;
based on comparison of the third plurality of FEC encoded signals and the at least one additional plurality of remodulated signals, selectively mark at least one portion of the third plurality of FEC encoded signals as at least one erasure to generate a fourth plurality of FEC encoded signals; and
decode the fourth plurality of FEC encoded signals to make at least one estimate of at least one information encoded therein.
6. The apparatus of claim 1 , wherein:
the apparatus is a transceiver that includes a transmitter.
7. An apparatus, comprising:
an input to receive a first Reed-Solomon (RS) encoded signal; and
a decoder to:
perform partial decoding of the first RS encoded signal to identify at least one error location therein;
based on the at least one error location, selectively mark at least one portion of the first RS encoded signal as at least one erasure to generate a second RS encoded signal; and
decode the second RS encoded signal to make an estimate of at least one information encoded within the second RS encoded signal.
8. The apparatus of claim 7 , wherein:
the first RS encoded signal is a first interleaved Reed-Solomon (RS) encoded signal including a plurality of codewords;
the second RS encoded signal is a second interleaved RS encoded signal; and
based on at least one error location within a first of the plurality of codewords, the decoder selectively to mark at least one portion of at least a second of the plurality of codewords to generate the second interleaved RS encoded signal.
9. The apparatus of claim 7 , wherein:
the input to receive a first plurality of RS encoded signals including the first RS encoded signal; and
the decoder to:
process the first plurality of RS encoded signals to generate a plurality of hard decisions;
remodulate the plurality of hard decisions to generate a plurality of remodulated signals;
based on comparison of the first plurality of RS encoded signals and the plurality of remodulated signals, selectively mark at least one portion of the first plurality of RS encoded signals as the at least one erasure to generate a second plurality of RS encoded signals including the second RS encoded signal; and
decode the second plurality of RS encoded signals to make at least one estimate of at least one information encoded within the second plurality of RS encoded signals including the estimate of the at least one information encoded within the second RS encoded signal.
10. The apparatus of claim 7 , wherein:
the input to receive the first RS encoded signal at or during a first time;
the input to receive a third RS encoded signal at or during a second time; and
the decoder to:
perform partial decoding of the third RS encoded signal to identify at least one error location therein;
based on the at least one error location within the third RS encoded signal, selectively mark at least one portion of the third RS encoded signal as at least one erasure to generate a fourth RS encoded signal; and
decode the fourth RS encoded signal to make an estimate of at least one information encoded within the fourth RS encoded signal.
11. The apparatus of claim 7 , further comprising:
a fidelity processor to generate at least one channel fidelity metric based on the at least one error location within the first RS encoded signal; and wherein:
the decoder to:
process the first plurality of RS encoded signals to generate a plurality of hard decisions;
based on the at least one error location and the at least one channel fidelity metric, selectively mark the at least one portion of the first RS encoded signal as the at least one erasure to generate the second RS encoded signal; and
decode the second RS encoded signal to make the estimate of the at least one information encoded within the second RS encoded signal.
12. The apparatus of claim 7 , wherein:
the apparatus is a transceiver that includes a transmitter.
13. An apparatus, comprising:
an input to receive a first forward error correction (FEC) encoded signal; and
a decoder to:
perform partial decoding of a first FEC encoded signal to identify at least one error location therein;
based on the at least one error location, selectively mark at least one portion of the first FEC encoded signal as at least one erasure to generate a second FEC encoded signal; and
decode the second FEC encoded signal to make an estimate of at least one information encoded within the second FEC encoded signal.
14. The apparatus of claim 13 , wherein:
the first FEC encoded signal is a first Reed-Solomon (RS) encoded signal; and
the second FEC encoded signal is a second RS encoded signal.
15. The apparatus of claim 13 , wherein:
the first FEC encoded signal is a first interleaved Reed-Solomon (RS) encoded signal including a plurality of codewords;
the second FEC encoded signal is a second interleaved RS encoded signal; and
based on at least one error location within a first of the plurality of codewords, the decoder selectively to mark at least one portion of at least a second of the plurality of codewords to generate the second interleaved RS encoded signal.
16. The apparatus of claim 13 , wherein:
the input to receive a first plurality of encoded signals including the first FEC encoded signal; and
the decoder to:
process the first plurality of FEC encoded signals to generate a plurality of hard decisions;
remodulate the plurality of hard decisions to generate a plurality of remodulated signals;
based on comparison of the first plurality of encoded signals and the plurality of remodulated signals, selectively mark at least one portion of the first plurality of encoded signals as the at least one erasure to generate a second plurality of encoded signals including the second FEC encoded signal; and
decode the second plurality of encoded signals to make at least one estimate of at least one information encoded within the second plurality of encoded signals including the estimate of the at least one information encoded within the second FEC encoded signal.
17. The apparatus of claim 13 , wherein:
the input to receive the first FEC encoded signal at or during a first time;
the input to receive a third FEC encoded signal at or during a second time; and
the decoder to:
perform partial decoding of the third FEC encoded signal to identify at least one error location therein;
based on the at least one error location within the third FEC encoded signal, selectively mark at least one portion of the third FEC encoded signal as at least one erasure to generate a fourth FEC encoded signal; and
decode the fourth FEC encoded signal to make an estimate of at least one information encoded within the fourth FEC encoded signal.
18. The apparatus of claim 13 , further comprising:
a fidelity processor to generate at least one channel fidelity metric based on the at least one error location within the first FEC encoded signal; and wherein:
the decoder to:
process the first plurality of FEC encoded signals to generate a plurality of hard decisions;
based on the at least one error location and the at least one channel fidelity metric, selectively mark the at least one portion of the first FEC encoded signal as the at least one erasure to generate the second FEC encoded signal; and
decode the second FEC encoded signal to make the estimate of the at least one information encoded within the second FEC encoded signal.
19. The apparatus of claim 13 , wherein:
the at least one portion of the first FEC encoded signal is a symbol or a bit of the first FEC encoded signal.
20. The apparatus of claim 13 , wherein:
the apparatus is a transceiver that includes a transmitter.