IP Library Granted Patent US 8,575,612
Granted Patent B2
US 8,575,612 · App. 13/461,798 · Granted Nov 5, 2013

Pixel structure

Inventors: Chien-Chih Lee (Hsin-Chu, TW); Pei-Yi Shen (Hsin-Chu, TW); Ching-Yang Cheng (Hsin-Chu, TW); Shu-Ming Huang (Hsin-Chu, TW)
Assignee: AU Optronics Corp.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,575,612
App. No.
13/461,798
Granted
Nov 5, 2013
Kind
B2
Abstract

The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.

Claims (17)

1. A pixel structure, comprising:

a substrate;

a gate, disposed on the substrate;

a patterned electrode, disposed on the substrate;

a first insulating layer, disposed on the substrate, the gate and the patterned electrode, and the first insulating layer having a first through hole exposing a part of the patterned electrode;

a common electrode, disposed on the first insulating layer and disposed corresponding to the patterned electrode;

a second insulating layer, disposed on the common electrode and the first insulating layer, and the second insulating layer having a second through hole disposed corresponding to the first through hole;

a semiconductor layer, disposed on the second insulating layer, and disposed corresponding to the gate;

a source and a drain, disposed on the semiconductor layer and the second insulating layer and disposed corresponding to two sides of the gate respectively, the drain comprising a first portion and a second portion, the first portion of the drain being connected to the second portion of the drain, the first portion of the drain being electrically connected to the patterned electrode via the first through hole and the second through hole, and the second portion of the drain extending onto the common electrode, wherein the patterned electrode and the common electrode partially overlap and are coupled with each other to form a first storage capacitor, and the second portion of the drain and the common electrode partially overlap and are coupled with each other to form a second storage capacitor;

a passivation layer, disposed on the second insulating layer, the semiconductor layer, the source and the drain, and the passivation layer having a third through hole exposing a part of the drain; and

a pixel electrode, disposed on the passivation layer, and the pixel electrode being electrically connected to the drain via the third through hole.

2. The pixel structure according to claim 1 , wherein the gate and the patterned electrode are constituted by a first metal layer.

3. The pixel structure according to claim 1 , wherein the common electrode is a second metal layer.

4. The pixel structure according to claim 1 , wherein the source and the drain are constituted by a third metal layer.

5. The pixel structure according to claim 1 , wherein the semiconductor layer comprises a semiconductor channel layer, and a heavily doped semiconductor layer disposed between the semiconductor channel layer and the source and between the semiconductor channel layer and the drain.

6. The pixel structure according to claim 1 , wherein the third through hole of the passivation layer exposes the second portion of the drain.

7. The pixel structure according to claim 6 , further comprising an organic layer, disposed between the passivation layer and the pixel electrode, and the organic layer having a fourth through hole disposed corresponding to the third through hole.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2025
From: AUO CORPORATION
To: NEOLAYER LLC
Reel/Frame 072266/0941 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2012
From: LEE, CHIEN-CHIH; SHEN, PEI-YI; CHENG, CHING-YANG; HUANG, SHU-MING
To: AU OPTRONICS CORP.
Reel/Frame 028139/0607 →
Priority Claims (1)
TW 100124773 A · Jul 13, 2011 · national
Continuity (1)
Related Publication 20130015449A1 · Jan 17, 2013