Granted Patent B2

US 8,314,443 · App. 13/461,874 · Granted Nov 20, 2012

Abstract

Claims (33)

1. A device comprising:

a semiconductor structure comprising:

a light emitting layer disposed between an n-type region and a p-type region;

an n-contact region and a p-contact region, wherein a cross section of the n-contact region comprises a plurality of first regions wherein portions of the light emitting layer and the p-type region are removed to expose the n-type region, wherein the plurality of first regions are separated by a plurality of second regions wherein second regions comprise a portion of the light emitting layer and a portion of the p-type region; and

a trench disposed between the n-contact region and the p-contact region;

a first metal contact formed over the semiconductor structure in the p-contact region; and

a second metal contact formed over the semiconductor structure in the n-contact region;

wherein the second metal contact is in electrical contact with at least one of the first regions in the n-contact region

wherein the first metal contact and the second metal contact are co-planer.

2. The device of claim 1 wherein the trench electrically isolates the first metal contact from the second metal contact.

3. The device of claim 1 wherein the plurality of first regions comprise holes formed in the semiconductor structure, wherein the holes are between one and five microns wide.

4. The device of claim 3 wherein centers of nearest neighbor holes are spaced between four and eight microns apart.

5. The device of claim 1 wherein the plurality of second regions comprise posts of semiconductor material.

6. The device of claim 5 wherein the posts are between one and five microns wide.

7. The device of claim 1 wherein a cross section of the second metal contact comprises a plurality of hills separated by valleys.

8. The device of claim 1 further comprising an insulating layer disposed on a sidewall of the trench.

9. A method comprising:

etching a semiconductor structure, the semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region, to form:

the n-contact region, wherein a cross section of the n-contact region comprises a plurality of first regions wherein portions of the light emitting layer and the p-type region are removed to expose the n-type region, wherein the plurality of first regions are separated by a plurality of second regions wherein second regions comprise a portion of the light emitting layer and a portion of the p-type region; and

forming a trench disposed between the n-contact region and the p-contact region;

forming a first metal contact over the p-contact region; and

forming a second metal contact over the n-contact region;

wherein the second metal contact is in electrical contact with at least one first regions of the n-contact region

wherein the first metal contact and the second metal contact are co-planer.

10. The method of claim 9 further comprising forming a plurality of metal bumps on the first metal contact.

11. The method of claim 10 further comprising bonding the semiconductor structure to a mount, wherein bonding comprises causing the plurality of metal bumps to collapse such that the collapsed bumps electrically and mechanically connect the semiconductor device to the mount and wherein the metal bumps remain in a solid phase during bonding.

12. The method of claim 10 wherein the plurality of metal bumps comprise a metal with a Young's modulus less than 150 GPa.

13. The method of claim 10 wherein:

the plurality of metal bumps each have a width between one and five microns and a height between one and five microns; and

nearest neighbor bumps are spaced between four and eight microns apart.

14. The method of claim 9 further comprising:

coating the device with an insulating layer; and

removing the insulating layer from the n-contact regions and the p-contact regions such that the insulating layer remains on a sidewall of the trench.

Assignments (8)