Lateral insulated-gate bipolar transistor and manufacturing method thereof
View Patent ↗A lateral insulated-gate bipolar transistor includes a buried insulation layer which opens only part of the collector ion implantation region and isolates the other regions, thereby reducing the loss by the turn-off time. The lateral insulated-gate bipolar transistor further includes a deep ion implantation region formed to face towards the open part of the collector ion implantation region, thereby decreasing the hole current injected into a base region under an emitter ion implantation region, and thereby greatly increasing the latch-up current level by relatively increasing the hole current injected into the deep ion implantation region having no latch-up effect.
1. A lateral insulated-gate bipolar, transistor, comprising:
a first conductive type semiconductor substrate;
a second conductive type drift region formed in the first conductive type semiconductor substrate;
a first conductive type collector ion implantation region formed at a preset depth in the second conductive type drift region;
a buried insulation layer formed to have at least one open area and at least one closed area on an interface between a top surface of the collector ion implantation region and the drift region;
a first conductive type base region formed to face towards a first open area of the at least one open area in the semiconductor substrate;
a gate electrode formed between adjacent first conductive type base regions on the semiconductor substrate;
a second conductive type emitter ion implantation region formed at side portions of the gate electrode in the semiconductor substrate;
an insulation layer formed on a top surface of the semiconductor substrate including the gate electrode,
a contact formed to penetrate the insulation layer and a first closed area of the at least one closed area of the buried insulation layer and contacting the collector ion implantation region;
an emitter electrode electrically connected to the emitter ion implantation region; and
a collector electrode electrically connected to the contact.
2. The lateral insulated-gate bipolar transistor of claim 1 , further comprising:
a first conductive type first ion implantation region formed in the first conductive type base region so as to be aligned with the first open area.
3. The lateral insulated-gate bipolar transistor of claim 2 , further comprising:
a first conductive type second ion implantation region formed at side portions of the emitter ion implantation region in the first ion implantation region.
4. The lateral insulated-gate bipolar transistor of claim 1 , wherein the buried insulation layer comprises an oxide film.
5. A method for manufacturing a lateral insulated-gate bipolar transistor, the method comprising:
forming a second conductive type drift region in a first conductive semiconductor substrate;
forming a first conductive type collector ion implantation region at a preset depth in the second conductive drift region;
forming a buried insulation layer having at least one open area and at least one closed area on an interface between a top surface of the collector ion implantation region and the drift region;
forming a first conductive type base region to face towards a first open area of the at least one open area in the semiconductor substrate;
forming a gate electrode between adjacent first conductive type base regions on the semiconductor substrate;
forming a second conductive type emitter ion implantation region at side portions of the gate electrode in the semiconductor substrate;
forming an insulation layer on a top surface of the semiconductor substrate including the gate electrode,
forming a contact which penetrates the insulation layer and a first closed area of the at least one closed area of the buried insulation layer and makes contact with the collector ion implantation region; and
forming an emitter electrode electrically connected to the emitter ion implantation region; and
forming a collector electrode electrically connected to the contact.
6. The method of claim 5 , further comprising:
after forming the first conductive type base region, forming a first conductive type first ion implantation region in the first conductive type base region so as to be aligned with the first open area.
7. The method of claim 6 , further comprising:
after forming the emitter ion implantation region, forming a first conductive type second ion implantation region at side portions of the emitter ion implantation region in the first ion implantation region.
8. The method of claim 5 , wherein the forming the buried insulation layer comprises:
forming a mask pattern defining the at least one open area and the at least one closed area on top of the semiconductor substrate; and
implanting oxygen ions in the at least one closed area using the mask pattern to form the buried insulation layer.