Accessing common registers in a multi-core processor

1. A system for accessing common registers in a register domain in a multi-core processor, comprising:

core logic provided at each of a plurality of processing cores in a core domain, the core logic streaming at least one transaction from the core domain to the register domain, wherein both the core domain and the register domain are different clock domains in the same multi-core processor; and

bus interface logic in the register domain, the bus interface logic reassembling the at least one streamed transaction for data access operations at the common registers.

2. The system of claim 1 further comprising a semaphore in the register domain, the semaphore arbitrating access by a plurality of processing cores to the common registers.

3. The system of claim 1 further comprising a switch in the core domain, the switch determining if the at least one transaction is addressed to the common registers or a core register.

4. The system of claim 1 wherein the bus interface logic includes a write staging register for writing data associated with a write transaction to the common registers.

5. The system of claim 1 further comprising a synchronizer between the core domain and the register domain, the synchronizer timing transfer of the at least one streamed transaction between the core domain and the register domain.

6. The system of claim 1 wherein the bus interface logic streams data read from the common registers in the register domain, and the core logic reassembles the streamed data in the core domain.

7. The system of claim 6 wherein the core logic includes a read buffer for reassembling the streamed data in the core domain.

8. The system of claim 6 further comprising a synchronizer between the core domain and the register domain, the synchronizer timing transfer of the streamed data between the register domain and the core domain.

9. The system of claim 1 , wherein core registers in the multi-core processor are linked to one another in a crab-chain arrangement.

10. The system of claim 9 , wherein the crab-chain arrangement is an interface between the core registers within each processing core.

11. The system of claim 9 , wherein transactions are issued as segments for delivery from one core register to a next core register in a chain arrangement.

12. The system of claim 9 , wherein the common registers are shared by two or more processing cores.

13. The system of claim 9 , wherein the different clock domains are different areas of the multi-core processor operating at different frequencies.

14. The system of claim 5 further comprising a throttling mechanism to issue a control signal to a write interface to discard transaction segments based on a threshold for a queue for the synchronizer.

15. A system for accessing common registers in a register domain in a multi-core processor, comprising:

means for transferring at least one transaction in segments from a core domain to a register domain, both the core domain and the register domain being different clock domains in the same multi-core processor; and

means for reassembling the at least one transaction in the register domain for data access operations at the common registers.

16. The system of claim 15 further comprising:

means for transferring data in segments from the register domain to the core domain; and

means for reassembling the data in the core domain.

17. The system of claim 15 further comprising means for arbitrating access to the common registers.

18. The system of claim 15 further comprising means for synchronizing the segments between the core domain and the register domain.

19. The system of claim 15 further comprising means for linking core registers in the multi-core processor.

20. The system of claim 19 wherein the means for linking is by crab chaining the core registers in the multi-core processor.