Method of fabricating a thin film transistor from amorphous silicon and organic light emitting diode display device having the thin film transistor
View Patent ↗A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain electrodes disposed on the pixel region, at least one gettering site disposed on the non-pixel region, and at least one connection portion to connect the at least one gettering site and the semiconductor layer. The method of fabricating the TFT includes patterning a polycrystalline silicon (poly-Si) layer to form a plurality of semiconductor layers, connection portions, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the connection portions, and annealing the substrate to getter the plurality of semiconductor layers.
1. A method of fabricating a thin film transistor (TFT), comprising:
forming an amorphous silicon (a-Si) layer on both a pixel region and a non-pixel region of a substrate;
crystallizing the a-Si layer with a metal catalyst to form a polycrystalline silicon (poly-Si) layer;
patterning the poly-Si layer to form a plurality of semiconductor layers, at least one connection portion, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the at least one connection portion;
annealing the substrate to getter the plurality of semiconductor layers;
forming a gate insulating layer on the substrate;
forming gate electrodes on the gate insulating layer respectively corresponding to channel regions of the plurality of semiconductor layers; and
forming source and drain electrodes electrically connected to the plurality of semiconductor layers and electrically insulated from the gate electrode.
2. The method according to claim 1 , wherein the at least one gettering site is formed in the non-pixel region.
3. The method according to claim 1 , wherein the semiconductor layers, the gate electrode, and the source and drain electrodes are formed in the pixel region.
4. The method according to claim 1 , wherein the metal catalyst includes one selected from the group consisting of nickel (Ni), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), tin (Sn), antimony (Sb), copper (Cu), terbium (Tb), and cadmium (Cd).
5. The method according to claim 1 , wherein the annealing is performed at a temperature of about 500 to 993° C. for 10 seconds to 10 hours.
6. The method according to claim 1 , wherein the annealing is performed at a temperature at or below the eutectic point of the metal catalyst.