Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system

1. A semiconductor memory device, comprising:

a system clock terminal configured to receive a system clock with a first frequency or a second frequency;

a data terminal provided to transfer a data therethrough;

a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough;

a command terminal provided to receive a command that communicates the data with an outside thereof; and

a preamble register configured to be capable of specifying a length of a preamble of the strobe signal prior to the communicating, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively, each of the first and second lengths being defined by a number of clock of the system clock.

2. The semiconductor memory device as claimed in claim 1 ,

wherein the length of the preamble is the first length when a first value is set in the preamble register.

3. The semiconductor memory device as claimed in claim 2 ,

wherein the length of the preamble is the second length different from the first length when a second value different from the first value is set in the preamble register.

4. The semiconductor memory device as claimed in claim 3 ,

wherein the first length is 1 CK of the system clock and the second length is 2 CK of the system clock.

5. The semiconductor memory device as claimed in claim 1 ,

wherein the strobe signal is outputted from the semiconductor memory device to supply the strobe signal to the outside in a read operation.

6. The semiconductor memory device as claimed in claim 1 , the device further comprising:

a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the strobe signal to communicate the data.

7. The semiconductor memory device as claimed in claim 6 ,

wherein the preamble comprises a read preamble, and the data strobe signal output control circuit outputs the toggle transition of the strobe signal to output the data.

8. The semiconductor memory device as claimed in claim 6 ,

wherein the data strobe signal output control circuit further outputs a postamble of the data strobe signal following to the toggle transition.

9. The semiconductor memory device as claimed in claim 1 , further comprising:

a DLL circuit; and

a DLL selection circuit that can select a DLL selection mode which sets the DLL circuit in an activate mode, and a DLL non-selection mode which sets the DLL circuit in a deactivate mode.

10. The semiconductor memory device as claimed in claim 9 ,

wherein the data is communicated based on the length of the preamble of the strobe signal in the deactivate mode.

11. The semiconductor memory device as claimed in claim 1 , further comprising a determination unit that determines a value tRPRE to be set in said preamble register, wherein said determination unit sets said value tRPRE as satisfying the condition that tse>0 in the following expression:

tse=tRPRE −( tDQSCK max− tDQSCK min),

where tDQSCKmax indicates a maximum value of a variation of a mismatch of falling and rising edges of a data strobe signal from a DSQ terminal of said semiconductor memory device with respect to falling and rising edges of a clock signal at a CK terminal of said semiconductor memory device and tDQSCKmin indicates a minimum value of said variation of mismatch.

12. A semiconductor memory device, comprising:

a system clock terminal configured to receive a system clock with a first frequency or a second frequency;

a data terminal provided to transfer a data therethrough;

a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough;

a command terminal provided to receive a command that communicates the data with an outside thereof;

a DLL circuit;

a DLL selection circuit that can select a DLL selection mode which sets the DLL circuit in an activate mode, and a DLL non-selection mode which sets the DLL circuit in a deactivate mode; and

a preamble register configured to be capable of specifying a length of a preamble of the strobe signal prior to the communicating, the length of the preamble including first and second lengths relating to the first and second frequencies, respectively, and the length of the preamble of the strobe signal in the deactivate mode being longer than the length of the preamble of the strobe signal in the activate mode, each of the first and second lengths being defined by a number of clock of the system clock.

13. The semiconductor memory device as claimed in claim 12 , wherein the length of the preamble is the first length when a first value is set in the preamble register.

14. The semiconductor memory device as claimed in claim 13 , wherein the length of the preamble is the second length different from the first length when a second value different from the first value is set in the preamble register.

15. The semiconductor memory device as claimed in claim 14 , wherein the first length is 1 CK of the system clock and the second length is 2 CK of the system clock.

16. The semiconductor memory device as claimed in claim 12 , wherein the strobe signal is outputted from the semiconductor memory device to supply the strobe signal to the outside in a read operation.

17. The semiconductor memory device as claimed in claim 12 , the device further comprising a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the strobe signal to communicate the data.

18. The semiconductor memory device as claimed in claim 17 , wherein the preamble comprises a read preamble, and the data strobe signal output control circuit outputs the toggle transition of the strobe signal to output the data.

19. The semiconductor memory device as claimed in claim 17 , wherein the data strobe signal output control circuit further outputs a postamble of the data strobe signal following to the toggle transition.

20. A semiconductor memory device, comprising:

a system clock terminal configured to receive a system clock having a frequency;

a data terminal provided to transfer a data therethrough;

a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough;

a command terminal provided to receive a command that communicates the data with an outside thereof; and

a preamble register configured to be capable of specifying a length of a preamble of the strobe signal prior to the communicating, the length of the preamble being changed based on the frequency of the system clock, the length being defined by a number of clock of the system clock.

21. The semiconductor memory device as claimed in claim 20 , wherein the more the frequency of the system clock is increased, the longer the length of the preamble is set in the register.

22. The semiconductor memory device as claimed in claim 20 , wherein the larger a CAS latency is, the longer the length of the preamble is set in the register.

23. The semiconductor memory device as claimed in claim 22 , wherein the length of the preamble is changed enough that a controller associated to the semiconductor memory device includes a gate opening area, which overlaps the length of the preamble, so that the controller can receive the data from the memory device.

24. The semiconductor memory device as claimed in claim 1 , wherein the first length is longer than the second length and the first frequency is higher than the second frequency.

25. The semiconductor memory device as claimed in claim 12 , wherein the first length is longer than the second length and the first frequency is higher than the second frequency.