SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM
A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.
1 . A controller, comprising:
a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data,
at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.
2 . The controller as claimed in claim 1 ,
wherein the length is one of 1 tCK and 2 tCK.
3 . The controller as claimed in claim 1 ,
wherein the command includes an address strobe signal, and a write enable signal.
4 . The controller as claimed in claim 1 ,
wherein the strobe signal comprises a data strobe signal.
5 . The controller as claimed in claim 4 ,
wherein the data strobe signal is transferred from the semiconductor memory device when performing a read operation.
6 . The controller as claimed in claim 1 ,
wherein the plurality of external terminals further supply a clock signal, a clock enable signal, and a chip select signal.
7 . The controller as claimed in claim 1 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
8 . The controller as claimed in claim 7 ,
wherein the preamble length determination unit determines the length of the preamble based on a variation of a delay time of the strobe signal.
9 . The controller as claimed in claim 7 ,
wherein the preamble length determination unit performs a data read test for the semiconductor memory device to determine the length of the preamble.
10 . The controller as claimed in claim 7 ,
wherein the preamble length determination unit configures to determine the length of the preamble at a system start-up time.
11 . The controller as claimed in claim 7 ,
wherein the preamble length determination unit configures to determine the length of the preamble for each fixed time interval.
12 . A controller, comprising:
a first external terminal configured to supply a system clock to a semiconductor memory device;
a second external terminal configured to supply a command to the semiconductor memory device;
a third external terminal configured to communicate a data with the semiconductor memory device;
a fourth external terminal configured to transmit a data strobe signal having a preamble and a toggle transition following to the preamble, the preamble corresponding to a start timing of communicating the data and the toggle transition corresponding to communicating the data between the controller and the semiconductor memory device; and
a fifth external terminal configured to be capable of outputting an information specifying a length of the preamble to the semiconductor memory device.
13 . The controller as claimed in claim 12 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
14 . The controller as claimed in claim 13 ,
wherein the preamble length determination unit determines the length of the preamble based on a frequency of the system clock.
15 . The controller as claimed in claim 12 ,
wherein the length is one of 1 tCK and 2 tCK.
16 . The controller as claimed in claim 12 ,
wherein the length comprises a first period in a first situation and a second period different from the first period in a second situation.
17 . A controller, comprising:
a first external terminal configured to communicate a data;
a second external terminal configured to communicate a data strobe signal related to the data, the data strobe signal including a preamble and a toggle transition following to the preamble, the data being transferred by the toggle transition of the data strobe signal through the first external terminal; and
a third external terminal configured to be capable of outputting an information which specifies a length of the preamble.
18 . The controller as claimed in claim 17 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
19 . The controller as claimed in claim 18 ,
wherein the preamble length determination unit determines the length of the preamble based on a frequency of the system clock.
20 . The controller as claimed in claim 17 , the controller further comprising:
a plurality of external terminals configured to output an address strobe signal, and a write enable signal.
21 . The controller as claimed in claim 20 ,
wherein the plurality of external terminals further outputs a clock signal, a clock enable signal, and a chip select signal.
22 . The controller as claimed in claim 17 ,
wherein the length is 1 tCK in a first situation and 2 tCK in a second situation.
23 . The controller as claimed in claim 17 ,
wherein the length comprises a first period in a first situation and a second period different from the first period in a second situation.