SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM
A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble resister configured to be capable of storing the information.
1 . A system, comprising:
a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and
a semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,
at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device,
the semiconductor memory device further comprising a preamble resister configured to be capable of storing the information.
2 . The system as claimed in claim 1 , the device further comprising:
a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.
3 . The system as claimed in claim 1 ,
wherein the length of the preamble is a first length when a first value is set in the preamble resister.
4 . The system as claimed in claim 3 ,
wherein the length of the preamble is a second length different from the first length when a second value different from the first length is set in the preamble resister.
5 . The system as claimed in claim 4 ,
wherein the first length is 1tCK and the second length is 2tCK.
6 . The system as claimed in claim 1 , the device further comprising:
a DLL circuit; and
a DLL selection circuit that can select a DLL selection mode which sets the DLL circuit in an activate mode, and a DLL non-selection mode which sets the DLL circuit in a deactivate mode.
7 . The system as claimed in claim 6 ,
wherein the data is communicated based on the length of the preamble in the deactivate mode.
8 . The system as claimed in claim 1 ,
wherein the data strobe signal is transferred from the semiconductor memory device to the controller when performing a read operation.
9 . The system as claimed in claim 1 , the controller further comprising:
a preamble length determination unit configured to determine the length of the preamble.
10 . The system as claimed in claim 9 ,
wherein the preamble length determination unit determines the length of the preamble based on a variation of a delay time of the strobe signal.
11 . The system as claimed in claim 10 ,
wherein the preamble length determination unit performs a data read test for the semiconductor memory device to determine the length of the preamble.
12 . The system as claimed in claim 11 ,
wherein the preamble length determination unit determines the length of the preamble at a system start-up time.
13 . The system as claimed in claim 11 ,
wherein the preamble length determination unit determines the length of the preamble for each fixed time interval.
14 . A system, comprising a semiconductor memory device and a controller,
the semiconductor memory device comprising:
a first external provided configured to receive a read command;
a second external terminal provided to output a data strobe signal in response to the read command, the data strobe signal including a read preamble and a toggle transition following to the preamble;
a third terminal provided to output a read data in synchronization with the toggle transition of the data strobe signal; and
a read preamble register that includes a bit area to store an information specifying a length of the read preamble of the data strobe signal,
the controller comprising:
a fourth external terminal provided to output the read command;
a fourth external terminal provided to receive the read data;
a fifth external terminal provided to receive the data strobe signal related to the read data; and
a sixth external terminal provided to be capable of outputting the information specifying the length of the read preamble.
15 . The system as claimed in claim 14 ,
wherein the length of the read preamble is set to a first length when the information indicates a first value.
16 . The system as claimed in claim 15 .
wherein the length of the read preamble is set to a second length different form the first length when the information indicates a second value different from the first value.
17 . The system as claimed in claim 14 , the semiconductor memory device further comprising:
a DLL circuit; and
a DLL selection circuit that can select a DLL selection mode which sets the DLL circuit in an activate mode, and a DLL non-selection mode which sets the DLL circuit in a deactivate mode,
wherein the read data is outputted based on the length of the preamble in the deactivate mode.
18 . The system as claimed in claim 14 , the controller further comprising:
a preamble length determination unit configured to determine the length of the read preamble.
19 . The system as claimed in claim 18 ,
wherein the preamble length determination unit performs a data read test for the semiconductor memory device to determine the length of the preamble.
20 . The system as claimed in claim 18 ,
wherein the preamble length determination unit determines the length of the preamble at a system start-up time.