Three-axis accelerometers and fabrication methods
View Patent ↗MEMS accelerometers have a substrate, and a proof mass portion thereof which is separated from the substrate surrounding it by a gap. An electrically-conductive anchor is coupled to the proof mass, and a plurality of electrically-conductive suspension anus that are separated from the proof mass extend from the anchor and are coupled to the substrate surrounding the proof mass. A plurality of sense and actuation electrodes are separated from the proof mass by gaps and are coupled to processing electronics. The fabrication methods use deep reactive ion etch bulk micromachining and surface micromachining to form the proof mass, suspension arms and electrodes. The anchor, suspension arms and electrodes are made in the same process steps from the same electrically conductive material, which is different from the substrate material.
1. A method of fabricating an accelerometer, comprising:
forming a patterned isolation layer disposed on a front side of a substrate;
forming a sacrificial layer on the substrate;
removing the sacrificial layer on the isolation layer;
forming a patterned low-resistivity structural layer on the front side of the substrate to define suspension arms, sense and actuation electrodes, and bond pads;
patterning the sacrificial layer on a back side of the substrate;
etching the back side of the substrate to expose the sacrificial layer disposed beneath the low-resistivity structural layer on the front side of the substrate and to define outer edge of a proof mass; and
releasing the proof mass by dissolving the sacrificial layer.
2. A method of fabricating an accelerometer, comprising:
providing a substrate;
forming an isolation layer on the substrate;
patterning the isolation layer disposed on a front side of the substrate;
forming a sacrificial layer on the substrate;
removing the sacrificial layer on the isolation layer;
etching anchor holes and bond pad contact windows through the isolation layer to expose the underlying substrate;
forming a low-resistivity structural layer on the substrate;
patterning the low-resistivity structural layer on the front side of the substrate to define suspension arms, sense and actuation electrodes, and bond pads;
patterning the sacrificial layer on a back side of the substrate if such is formed;
etching the back side of the substrate to expose the sacrificial layer disposed beneath the low-resistivity structural layer on the front side of the substrate and to define outer edge of a proof mass; and
releasing the proof mass by dissolving the sacrificial layer.
3. The method recited in claim 2 wherein the sacrificial layer comprises oxide, and etching the back side of the substrate comprises dry reactive ion etching.
4. The method recited in claim 2 wherein the substrate comprises a semiconductor substrate.
5. The method recited in claim 2 wherein the substrate comprises a silicon substrate.
6. The method recited in claim 2 wherein the substrate comprises a semiconductor-on-insulator substrate.
7. The method recited in claim 2 wherein the substrate comprises a metal in which deep trenches may be fabricated by reactive ion etching.
8. The method recited in claim 2 wherein the structural layer comprises a semiconductor layer.
9. The method recited in claim 2 wherein the structural layer comprises doped polysilicon.
10. The method recited in claim 2 wherein the structural layer comprises metal.
11. The method recited in claim 2 wherein the sacrificial layer comprises oxide, and etching the back side of the substrate comprises dry reactive ion etching.
12. The method recited in claim 2 wherein the substrate comprises a semiconductor substrate.
13. The method recited in claim 2 wherein the substrate comprises a silicon substrate.
14. The method recited in claim 2 wherein the substrate comprises a semiconductor-on-insulator substrate.
15. The method recited in claim 2 wherein the substrate comprises a metal in which deep trenches may be fabricated by reactive ion etching.
16. The method recited in claim 2 wherein the structural layer comprises a semiconductor layer.
17. The method recited in claim 2 wherein the structural layer comprises doped polysilicon.
18. The method recited in claim 2 wherein the structural layer comprises metal.