Fractional-N phase locked loop based on bang-bang detector
View Patent ↗The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.
1. A phase-locked loop (PLL) for maintaining, a phase relationship between an output signal and an input signal, the PLL comprising:
a multi-modulus divider (MMD) configured to reduce a frequency of the output signal by a fractional division factor to provide a comparison signal;
a modulator configured to increment an accumulator value after a cycle of the comparison signal and control the MMD based on the accumulator value to alternately reduce the frequency of the output signal by at least two integer division factors to provide the comparison signal;
a delay line configured to delay the comparison signal based on the accumulator value to provide an adjusted comparison signal; and
a bang-bang phase detector (BBPD) configured to detect a difference in phase between the input signal and the adjusted comparison signal to adjust a phase of the output signal to maintain the phase relationship.
2. The PLL of claim 1 , wherein the delay line comprises:
a plurality of series coupled delay stages configured to delay the comparison signal based on a control signal to provide the adjusted comparison signal.
3. The PLL of claim 2 , wherein at least one of the delay stages is configured to be bypassed based on the control signal.
4. The PLL of claim 2 , wherein at least one of the delay stages comprises a plurality of delay elements coupled in parallel and individually enabled and disabled by the control signal.
5. The PLL of claim 4 , wherein the plurality of delay elements are scaled in size to provide different drive strengths.
6. The PLL of claim 1 , wherein the delay line comprises:
an adjustable capacitive load configured to be adjusted based on a control signal.
7. The PLL of claim 1 , wherein the delay line comprises:
a decoder configured to convert the accumulator value into a control signal such that the comparison signal is delayed by an amount determined based on the accumulator value.
8. The PLL of claim 1 , further comprising:
a digital filter configured to low-pass filter the difference in phase.
9. The PLL of claim 1 , further comprising:
a digitally controlled oscillator configured to provide the output signal and adjust the frequency of the output signal based on the difference in phase.
10. The PLL of claim 1 , wherein the MMD is a dual modulus divider and the modulator is a first order delta sigma modulator.
11. The PLL of claim 1 , wherein the BBPD is a three-level output BBPD.
12. A phase-locked loop (PLL) for maintaining a phase relationship between an output signal and an input signal, the PLL comprising:
a multi-modulus divider (MMD) configured to reduce a frequency of the output signal by a fractional division factor to provide a comparison signal;
a modulator configured to increment an accumulator value after a cycle of the comparison signal;
a delay line configured to delay the comparison signal based on the accumulator value to provide an adjusted comparison signal; and
a bang-bang phase detector (BBPD) configured to provide a three-level output signal that indicates whether a phase of the input signal is leading, lagging or substantially in sync with a phase of the adjusted comparison signal.
13. The PLL of claim 12 , wherein the delay line comprises:
a plurality of series coupled delay stages configured to delay the comparison signal based on a control signal to provide the adjusted comparison signal.
14. The PLL of claim 13 , wherein at least one of the delay stages is configured to be bypassed based on the control signal.
15. The PLL of claim 13 , wherein at least one of the delay stages comprises a plurality of delay elements coupled in parallel and individually enabled and disabled by the control signal.
16. The PLL of claim 12 , wherein the delay line comprises:
an adjustable capacitive load configured to be adjusted based on a control signal.
17. The PLL of claim 12 , wherein the delay line comprises:
a decoder configured to convert the accumulator value into a control signal such that the comparison signal is delayed by an amount determined based on the accumulator value.
18. A phase-locked loop (PLL) for maintaining a phase relationship between an output signal and an input signal, the PLL comprising:
a multi-modulus divider (MMD) configured to reduce a frequency of the output signal by a fractional division factor to provide a comparison signal;
a modulator configured to increment an accumulator value after a cycle of the comparison signal;
a delay line configured to delay the comparison signal based on the accumulator value, using a plurality of series coupled delay stages, to provide an adjusted comparison signal; and
a flip-flop configured to detect a difference in phase between the input signal and the adjusted comparison signal to adjust a phase of the output signal to maintain the phase relationship.
19. The PLL of claim 18 , wherein the delay line comprises:
a decoder configured to convert the accumulator value into a control signal such that the comparison signal is delayed by an amount determined based on the accumulator value.