Punch-through semiconductor device and method for producing same
View Patent ↗A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration N D , a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 kV cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage V pt of the semiconductor device is between 70% and 99% of a break down voltage V bd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.
1. A maximum-punch-through semiconductor device having at least a two-layer structure comprising:
a collector metallization on a collector side;
an emitter metallization on an emitter side, which lies opposite the collector side;
a base layer of a first conductivity type arranged between the emitter metallization and the collector metallization, and having a predetermined doping concentration N D ;
a channel region of a second conductivity type arranged between the base layer and the emitter metallization;
a buffer layer of the first conductivity type arranged between the base layer and the collector metallization, wherein the buffer layer has a thickness of between about 1 μm to about 3 μm and a peak doping concentration which is higher than a doping concentration of the base layer, a thickness W of the base layer being determined by:
W
=
V
bd
+
V
pt
4010
kV
cm
-
5
/
8
*
(
N
D
)
1
/
8
wherein a punch-through voltage V pt of the semiconductor device is between 70% and 99% of a break down voltage V bd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.
2. The semiconductor device of claim 1 , wherein the punch-through voltage V pt of the semiconductor device is between 75% and 99% of the break down voltage V bd of the semiconductor device.
3. The semiconductor device of claim 1 , wherein the buffer layer is arranged such that an electric field at an interface between the base layer and the buffer layer is below 40 kV/cm.
4. The semiconductor device of claim 1 , wherein the peak doping concentration of the buffer layer is above 1*10 15 cm −3 .
5. The semiconductor device of claim 1 , wherein the break down voltage of the semiconductor device is below 2500 V.
6. The semiconductor device of claim 1 , wherein the semiconductor device is an insulated gate bipolar transistor with a source region of the first conductivity type between the channel region and the emitter metallization.
7. The semiconductor device of claim 1 , wherein the semiconductor device is a diode with the buffer layer formed as a diode cathode layer, the channel region formed as an anode layer, the emitter metallization formed as a diode anode metallization and the collector metallization formed as a cathode metallization.
8. A method for producing a maximum-punch-through semiconductor device having at least a two-layer structure with layers of different conductivity types, the method comprising, in the following order:
(a) providing a wafer of a first conductivity type, having a first emitter side in a finalized semiconductor device, and a second side lying opposite the first side, and which wafer has a doping concentration N D ;
(b) producing a channel region of a second conductivity type on the first side; and
(c) applying particles of the first conductivity type to the wafer on the second side, which particles form a buffer layer in the finalized semiconductor device, wherein that part of the wafer with unamended doping concentration in the finalized semiconductor device forms a base layer, and the buffer layer has a peak doping concentration higher than the doping concentration of the wafer, and wherein a thickness of the base layer is selected such that:
W
=
V
bd
+
V
pt
4010
kV
cm
-
5
/
8
*
(
N
D
)
1
/
8
,
wherein a punch-through voltage V pt of the semiconductor device is between 70% and 99% of a break down voltage V bd of the semiconductor device.
9. The method of claim 8 , wherein in step (c), the buffer layer is created such the buffer layer extends only to such a depth of the wafer from the second side that the electric field is lower than 40 kV/cm.
10. The method of claim 8 , comprising after step (b):
thinning the wafer on the second side to a predetermined thickness.
11. The method of claim 8 , comprising in step (c):
applying particles of the first conductivity type by implanting n-type particles or hydrogen particles with a dose higher than 1*10 12 cm−2 and with energies higher than 100 keV.
12. The method of claim 8 , adapted for producing an insulated gate bipolar transistor and comprising after step (c):
(d) applying particles of the second conductivity type to the wafer on the second side, by implantation or deposition, which particles form a collector layer in the finalized semiconductor device.
13. The method of claim 12 , comprising in step (d):
applying the particles of the second conductivity type by implanting p-type particles with a dose higher than 1*10 12 cm −2 and with energies higher than 10 keV.
14. The method of claim 8 , comprising after step (c):
thermal annealing at temperatures below 500° C. or laser annealing.
15. The semiconductor device of claim 1 , wherein the punch-through voltage V pt of the semiconductor device is between 80% and 95% of the break down voltage V bd of the semiconductor device.
16. The semiconductor device of claim 1 , wherein the buffer layer is arranged such that an electric field at an interface between the base layer and the buffer layer is below 12 kV/cm.
17. The semiconductor device of claim 1 , wherein the peak doping concentration of the buffer layer is above 1*10 17 cm −3 .
18. The semiconductor device of claim 1 , wherein a thickness of the buffer layer is between 2 μm and 3 μm.
19. The semiconductor device of claim 1 , wherein the break down voltage of the semiconductor device is below 2000 V.