Semiconductor device isolation using an aligned diffusion and polysilicon field plate
An isolation structure prevents inter-device and intra-device leakage in first and second adjacent semiconductor devices in a substrate. The first and second semiconductor devices each include a gate region and at least one active region. A first channel stop region is configured to surround the first semiconductor device. A second channel stop region is configured to surround the second semiconductor device. A first field plate is located above at least part of the first channel stop region, and overlaps the gate region of the first semiconductor device in a first overlap region. A second field plate is located above at least part of the second channel stop region, and overlaps the gate region of the second semiconductor device in a second overlap region.
1. An isolation structure for preventing inter-device and intra-device leakage in first and second adjacent semiconductor devices in a substrate, the first and second semiconductor devices each comprising a gate region and at least one active region, the structure comprising:
a first channel stop region configured to surround the first semiconductor device;
a second channel stop region configured to surround the second semiconductor device;
a first field plate located above at least part of the first channel stop region, the first field plate overlapping the gate region of the first semiconductor device in a first overlap region; and
a second field plate located above at least part of the second channel stop region, the second field plate overlapping the gate region of the second semiconductor device in a second overlap region.
2. The isolation structure of claim 1 , wherein the first and second semiconductor devices are MOS transistors each comprising a polysilicon gate region, a source region and a drain region.
3. The isolation structure of claim 1 , wherein the first and second field plates and the first and second channel stop regions are held at a common potential.
4. The isolation structure of claim 1 , wherein the first and second field plates are composed of polysilicon.
5. The isolation structure of claim 1 , wherein a doping concentration of the first and second channel stop regions is greater than 5×10 18 cm −3 .
6. The isolation structure of claim 1 , wherein the first and second channel stop regions have a width in the range of 0.18 to 0.50 microns.
7. The isolation structure of claim 2 , wherein the first and second channel stop regions are separate from the source and drain regions of the MOS transistors by a distance that is determined by the maximum operating voltage of the MOS transistors.
8. The isolation structure of claim 2 , wherein the first and second channel stop regions are created by using implants for the source and drain regions of the MOS transistors.
9. The isolation structure of claim 1 , wherein the first and second overlap regions are about 0.5 microns.
10. The isolation structure of claim 1 , wherein a thickness of dielectric material between each gate region of the first and second MOS transistors and a respective one of the first and second field plate is in the range of 20 to 300 nanometers.
11. The isolation structure of claim 1 , wherein the first channel stop region and the second channel stop region are separated from one another between the first and second semiconductor devices.
12. The isolation structure of claim 1 , wherein the first channel stop region and the second channel stop region share a region between the first and second semiconductor devices.
13. The isolation structure of claim 1 , wherein the first field plate and the second field plate are separated from one another between the first and second semiconductor devices.
14. The isolation structure of claim 1 , wherein the first field plate and the second field plate share a region between the first and second semiconductor devices.