IP Library Granted Patent US 8,664,042
Granted Patent B2
US 8,664,042 · App. 13/471,009 · Granted Mar 4, 2014

Method for fabrication of configurable systems

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Quick Facts
Patent No.
US 8,664,042
App. No.
13/471,009
Granted
Mar 4, 2014
Kind
B2
Abstract

A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Claims (49)

1. A method to construct configurable systems, the method comprising:

providing a first configurable system comprising a first die and a second die,

wherein the connections between said first die and said second die comprise through-silicon-via (“TSV”),

wherein said first die is diced from a first wafer using first dice lines;

providing a second configurable system comprising a third die and a fourth die,

wherein the connections between said third die and said fourth die comprise through-silicon-via (“TSV”),

wherein said third die is diced from a third wafer using third dice lines; and

processing said first wafer and said third wafer utilizing at least 20 masks that are the same;

wherein said first dice lines are substantially different than said third dice lines, and

wherein said second die comprises a configurable I/O to connect said first configurable system to external devices.

2. The method to construct configurable systems according to claim 1 , wherein said first die is a field programmable gate array (FPGA) die.

3. The method to construct configurable systems according to claim 1 , wherein said fourth die comprises a configurable I/O die.

4. The method to construct configurable systems according to claim 1 , wherein said first die comprises a configurable memory die.

5. The method to construct configurable systems according to claim 1 , wherein said first die comprises a repeating array of functional units.

6. The method to construct configurable systems according to claim 1 , wherein said first die comprises a repeating array of functional units, wherein each of said functional units comprises a micro controller unit (MCU).

7. The method to construct configurable systems according to claim 1 , wherein said first die comprises unused dice lines.

8. The method to construct configurable systems according to claim 1 , wherein said diced comprises an etch step to define dice lines as a post process step.

9. A method to construct configurable systems, the method comprising:

providing a first configurable system comprising a first die and a second die;

wherein the connections from said first die to said second die comprise through-silicon vias (TSV),

wherein said first die is diced from a first wafer using first dice lines,

wherein said first dice lines are selected from a plurality of predefined potential dice lines, and

wherein said first die comprises unused dice lines, and

wherein said second die comprises unused dice lines,

providing a second configurable system comprising a third die and a fourth die,

wherein the connections between said third die and said fourth die comprise through-silicon-vias (“TSV”),

wherein said third die is diced from a third wafer using third dice lines; and

processing said first wafer and said third wafer utilizing at least 20 masks that are the same;

wherein said first dice lines are substantially different than said third dice lines.

10. A method to construct configurable systems according to claim 9 , wherein said second die comprises a configurable memory.

11. A method to construct configurable systems according to claim 9 , wherein said first die is a field programmable gate array (FPGA) die.

12. A method to construct configurable systems according to claim 9 , wherein said first die comprises a configurable I/O die.

13. A method to construct configurable systems, the method comprising:

providing a first configurable system comprising a first die and a second die, wherein the connections between said first die and said second die comprise through-silicon-via (“TSV”),

wherein said first die is diced from a first wafer using first dice lines;

providing a second configurable system comprising a third die and a fourth die,

wherein the connections between said third die and said fourth die comprise through-silicon-via (“TSV”),

wherein said third die is diced from a third wafer using third dice lines; and

processing said first wafer and said third wafer utilizing at least 20 masks that are the same;

wherein said first dice lines are substantially different than said third dice lines, and

wherein said second die comprises a configurable I/O to connect said first configurable system to external devices, and

wherein said fourth die comprises a SerDes circuit.

14. The method to construct configurable systems according to claim 13 , wherein said first die is a field programmable gate array (FPGA) die.

15. The method to construct configurable systems according to claim 13 , wherein said fourth die comprises a configurable I/O die.

16. The method to construct configurable systems according to claim 13 , wherein said first die comprises a configurable memory die.

17. The method to construct configurable systems according to claim 13 , wherein said first die comprises a repeating array of functional units.

18. The method to construct configurable systems according to claim 13 , wherein said first die comprises a repeating array of functional units, and wherein each of said functional units comprises a micro controller unit (MCU).

19. The method to construct configurable systems according to claim 13 , wherein said diced comprises an etch step to define dice lines as a post process step.

20. The method to construct configurable systems according to claim 13 , wherein said first die comprises unused dice lines.