Storage devices with soft processing
View Patent ↗A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
1. A storage device comprising:
a storage array including a plurality of storage elements, each storage element operable to be written to one of a discrete set of physical states;
a read circuit for selecting one or more storage elements and generating, for each selected storage element, an analog signal representative of the physical state of the selected storage element; and
an analog signal processing circuit for processing the analog signal to generate a plurality of outputs, each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
2. The storage device of claim 1 , wherein each output of the signal processing circuit includes a continuous-valued signal.
3. The storage device of claim 1 , further comprising a second signal processing circuit for processing the plurality of outputs of the signal processing circuit to generate a digital representation of a stored value of the selected storage element.
4. The storage device of claim 1 further comprising a control circuit coupled to the signal processing circuit, the control circuit being configured for generating a control signal to change a mapping characteristic from the analog signal generated by the read circuit to the set of outputs.
5. The storage device of claim 4 , wherein the control circuit is configured for changing the mapping characteristic based on an expected degree of variability of the analog signal generated by the read circuit.
6. The storage device of claim 5 , wherein the expected degree of variability includes noise variance.
7. The storage device of claim 1 , wherein each output of the signal processing circuit represents a probability of the selected storage element being at a respective one of the discrete set of physical states.
8. The storage device of claim 1 , wherein each one of the discrete set of physical states corresponds to a respective storage value.
9. The storage device of claim 8 , wherein each storage value corresponds to a bit string.
10. The storage device of claim 9 , wherein each output of the signal processing circuit represents a probability of a respective digit of the bit string having the value of “1.”
11. The storage device of claim 1 , wherein the storage array includes a plurality of floating-gate memory cells.
12. The storage device of claim 1 , wherein the storage array includes a plurality of dynamic random access memory (DRAM) cells.
13. The storage device of claim 1 , wherein the storage array includes a plurality of capacitive elements.
14. The storage device of claim 13 , wherein each capacitive element include one or more capacitors.
15. The storage device of claim 1 , wherein the read circuit is further configured to apply a reference voltage to the selected storage element to generate the analog signal representative of the physical state of the selected storage element.
16. The storage device of claim 1 , wherein the analog signal is a current-encoded signal.
17. The storage device of claim 1 , wherein the analog signal is a voltage-encoded signal.
18. The storage device of claim 1 , wherein the analog signal is a single-ended signal.
19. The storage device of claim 1 , wherein the analog signal is a differential signal.
20. The storage device of claim 1 , wherein each output of the signal processing circuit represents the degree of the association as a probability representation in a linear domain.
21. The storage device of claim 1 , wherein each output of the signal processing circuit represents the degree of the association as a probability representation in a log domain.
22. The storage device of claim 21 , wherein each output of the signal processing circuit includes a log probability based representation.
23. The storage device of claim 21 , wherein each output of the signal processing circuit includes a log likelihood ratio based representation.
24. The storage device of claim 1 , wherein the signal processing circuit includes a digital processing logic for processing binary representations determined from the analog signal.
25. The storage device of claim 1 , further comprising a non-linear signal transformation circuit coupled between the read circuit and the signal processing circuit.
26. A storage device comprising:
a storage array including a plurality of storage elements, each storage element operable to be written to one of a discrete set of physical states;
a read circuit for selecting one or more storage elements and generating, for each selected storage element, an analog signal representative of the physical state of the selected storage element; and
an analog signal processing circuit including:
a first module for processing the analog signal to generate a set of one or more outputs, each output representing a degree of an association of the selected storage element with a subset of one or more of the discrete set of physical states; and
a second module for processing the set of one or more outputs of the first module to generate a digital representation of a stored value of the selected storage element.
27. The storage device of claim 26 , wherein each output of the first module is a continuous-valued signal.
28. The storage device of claim 26 , wherein the second module includes an analog decoder core configured for, in each of a plurality of cycles of a decoding operation, accepting a portion of code data and a portion of an intermediate value data to generate an output.
29. The storage device of claim 28 , wherein the second module further includes an analog storage for storing the output of the analog decoder core.
30. The storage device of claim 29 , wherein the second module further includes an output section for combining data, including intermediate value data from the analog storage, to form decoded data representing an error correction of the code data.