Method and system for an integrated host PCI I/O bridge and dual port gigabit ethernet controller
View Patent ↗Embodiments may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.
1. A system comprising:
an inter-module bus interface;
an I/O bridge integrated within a single chip that is configured to control transfer of data across the inter-module bus interface;
a first bus controller integrated within the I/O bridge, wherein the I/O bridge is further configured to manage at least the inter-module bus interface via at least the first bus controller;
a second bus controller integrated within the I/O bridge, wherein the I/O bridge is further configured to manage an Ethernet interface via at least the second bus controller; and
a multiport Ethernet controller integrated within the single chip, wherein ports of the multiport Ethernet controller are assigned individual function identifiers.
2. The system of claim 1 , wherein the Ethernet interface is configured to independently process at least a first Ethernet network connection and a second Ethernet network connection.
3. The system of claim 1 , wherein the first bus controller comprises a primary PCI bus controller.
4. The system of claim 3 , wherein the second bus controller comprises a secondary PCI bus controller.
5. The system of claim 1 , the integrated multiport Ethernet controller further comprising:
at least two Ethernet controllers; and
a common arbiter, wherein:
the at least two Ethernet controllers share the common arbiter;
the common arbiter is coupled to a single bus interface, wherein
the single bus interface is further coupled to the I/O bridge; and
the common arbiter controls access to the single bus interface by the at least two Ethernet controllers.
6. The system of claim 5 , wherein the single bus interface comprises one selected from a group consisting of a PCI interface and a PCI-X interface.
7. The system of claim 1 , wherein the I/O bridge is coupled to a host system.
8. The system of claim 5 , further comprising:
a timing function module integrated within the single chip, wherein the timing function module is coupled to at least one of the I/O bridge, the at least two Ethernet controllers, or an I/O function module.
9. The system of claim 5 , wherein each of the Ethernet controllers has its own associated register blocks and memories.
10. The system of claim 1 , wherein the function identifier comprises a combination of a bus ID, device ID, and function ID.