Low-flux and low-noise detection circuit having a readout circuit with shielded integration node

1. A detection circuit comprising:

a photodiode connected to an integration node,

a biasing circuit for biasing the photodiode between a first reverse-bias state and a second floating state so as to form a Source Follower per Detector,

a readout circuit connected to the integration node for generating a signal representative of the scene observed by the photodiode,

a metal shielding arranged around the integration node and connected to an output of the readout circuit configured to have a potential varying in a same way as a potential at the integration node and form an electric shielding, wherein

the photodiode is made on a first substrate, the biasing circuit and the readout circuit are made on a second substrate, the photodiode being connected to the biasing circuit and the readout circuit by means of an electric contact, the electric contact being surrounded by a metal ring connected to an output of the readout circuit.

2. Detection circuit according to claim 1 , wherein the readout circuit comprises a follower transistor having an electrode connected to an electric node configured to have a potential varying in the same direction as the potential at the integration node.

3. Detection circuit according to claim 1 , wherein the metal shielding is connected to an output of the readout circuit configured to have a constant potential difference relative to the potential at the integration node.

4. Detection circuit according to claim 1 , wherein the metal shielding surrounds the electric power line connecting the photodiode to the biasing circuit.

5. Detection circuit according to claim 1 , wherein the metal shielding surrounds the electric power line connecting the integration node to the readout circuit.

6. Detection circuit according to claim 1 , wherein the metal shielding is arranged in an electrically insulating material, between the electric contact and the semiconductor substrate comprising the readout circuit.

7. Detection circuit according to claim 1 , wherein the retention node is a capacitive retention node configured to store electric charges emitted by the photodiode and causing shifting of the potential of the retention node from reverse-bias to forward-bias.

8. Detection matrix including a plurality of circuits according claim 1 , wherein each readout circuit comprising a specific selecting input, an output line being connected to the output terminal of the readout circuits.

9. Detection circuit according to claim 2 , wherein the follower transistor has a control electrode connected to the integration node and another electrode connected to the metal shielding.

10. Detection matrix according to claim 7 , wherein the output line is connected to the metal shielding.

11. A detection circuit comprising:

a photodiode connected to a capacitive integration node,

a biasing circuit for biasing the photodiode between a first reset state wherein the photodiode is reverse-biased and a second acquisition state wherein the photodiode is in a floating state so as to form a Source Follower per Detector,

a readout circuit connected to the integration node for generating a signal representative of the scene observed by the photodiode, the readout circuit being coupled to the integration node during the acquisition state,

a shielding made of conducting material arranged around the integration node and connected to an output of the readout circuit configured to have a potential varying in a same way as a potential at the integration node, wherein

the photodiode is made on a first substrate, the biasing circuit and the readout circuit are made on a second substrate, the photodiode being connected to the biasing circuit and the readout circuit by means of an electric contact, the electric contact being surrounded by a metal ring connected to an output of the readout circuit.