IP Library Granted Patent US 8,754,485
Granted Patent B2
US 8,754,485 · App. 13/477,632 · Granted Jun 17, 2014

3-dimensional non-volatile memory device including a selection gate having an L shape

Inventors: Ki Hong Lee (Gyeonggi-do, KR); Seung Ho Pyi (Gyeonggi-do, KR); Sung Chul Shin (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
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Quick Facts
Patent No.
US 8,754,485
App. No.
13/477,632
Granted
Jun 17, 2014
Kind
B2
Abstract

A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed.

Claims (20)

1. A 3-dimensional (3-D) non-volatile memory device, comprising:

a channel protruding from a substrate;

a selection gate formed on sidewall of the channel and having an L shape; and

a gate insulating layer interposed between the channel and the selection gate and surrounding the channel; and the selection gate includes a first region surrounding a side wall of the first channel and a second region protruding from the first region.

2. The 3-D non-volatile memory device of claim 1 , wherein impurities are doped onto the top and sidewalls of the channel.

3. The 3-D non-volatile memory device of claim 1 , further comprising memory cells formed over or under the selection gate and stacked along the channel.

4. A 3 -D non-volatile memory device, comprising:

a pair of channels protruding from a substrate;

selection gates formed on sidewalls of each of the channels and having an L shape;

a pipe channel coupled to bottoms of the pair of the channels ;

gate insulating layers interposed between the channels and the selection gates; and

memory cells formed under each of the selection gates and stacked along the channels; and the selection gate includes a first region surrounding a side wall of the first channel and a second region protruding from the first region.

5. The 3-D non-volatile memory device of claim 4 , wherein each of the channels and the pipe channel has a hole formed along a central axis, and the hole is filled with an insulating layer and a conductive plug formed on the insulating layer.

6. A 3-dimensional (3-D) non-volatile memory device, comprising:

a first channel column including a plurality of first channels protruding from a substrate;

a gate line formed on sidewalls of the plurality of the first channels and coupling the first channels included in one first channel column, wherein the gate line has an L shape; and

a plurality of gate insulating layers interposed between the plurality of the first channels and the gate line respectively; and the gate line includes first regions surrounding side walls of the first channels and a second region formed between the first channels and coupling the first regions.

7. The 3-dimensional (3-D) non-volatile memory device of claim 6 , further comprising:

a second channel column including a plurality of second channels.

8. The 3-dimensional (3-D) non-volatile memory device of claim 7 , wherein the gate line includes first region surrounding side walls of the first and second channels and a second region formed between the first and second channels and coupling the first regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2012
From: LEE, KI HONG; PYI, SEUNG HO; SHIN, SUNG CHUL
To: SK HYNIX INC.
Reel/Frame 028249/0548 →
Priority Claims (1)
KR 10-2011-0049021 · May 24, 2011 · national
Continuity (1)
Related Publication 20120299117A1 · Nov 29, 2012