Vertical IGBT adjacent a RESURF region

1. A semiconductor apparatus comprising a semiconductor substrate, wherein:

the semiconductor substrate comprises a device region in which a vertical type IGBT is formed and a peripheral region located around the device region,

an emitter region, a first semiconductor region, a stopper region, a drift region, a collector region, and a gate electrode are formed within the device region,

the emitter region is of an n-type and exposed at an upper surface of the semiconductor substrate;

the first semiconductor region is of a p-type, a part of the first semiconductor region is exposed at the upper surface of the semiconductor substrate, the first semiconductor region is in contact with the emitter region from an underside;

the stopper region is an epitaxial layer, of the n-type, in contact with the first semiconductor region from an underside, and separated from the emitter region by the first semiconductor region;

the drift region is of n-type and located under the stopper region, the drift region has a concentration of n-type impurities lower than a concentration of the n-type impurities in the stopper region;

the collector region is of p-type and in contact with the drift region from an underside; and

the gate electrode is in contact via an insulating film with the first semiconductor region in a range separating the stopper region from the emitter region,

a second semiconductor region, a third semiconductor region, and a fourth semiconductor region are formed within the peripheral region,

the second semiconductor region is of the p-type, has a concentration of p-type impurities lower than a concentration of the p-type impurities in the first semiconductor region, is exposed at the upper surface of the semiconductor substrate, and is consecutive with the first semiconductor region directly or via another semiconductor region having the p-type,

the third semiconductor region is an epitaxial layer, of the n-type, the third semiconductor region has a concentration of the n-type impurities equal to a concentration of the n-type impurities in the stopper region, the third semiconductor region is in contact with the second semiconductor region from an underside and extends such that it is exposed at the upper surface of the semiconductor substrate at a position adjacent to the second semiconductor region, and

the fourth semiconductor region is of the n-type, has a concentration of the n-type impurities lower than a concentration of the n-type impurities in the third semiconductor region, and is in contact with the third semiconductor region from an underside.

2. A semiconductor apparatus of claim 1 , wherein

a fifth semiconductor region is formed within the peripheral region, and

the fifth semiconductor region is of the n-type, has a concentration of the n-type impurities lower than the concentration of the n-type impurities in the third semiconductor region, is exposed at the upper surface of the semiconductor substrate, is located between the second semiconductor region and a side surface of the semiconductor substrate, and is in contact with the second semiconductor region from a lateral side.

3. A semiconductor apparatus of claim 1 , wherein the maximum value of the concentration of the p-type impurities in the second semiconductor region is higher than the maximum value of the concentration of the n-type impurities in the third semiconductor region.

4. A semiconductor apparatus of claim 1 , wherein within the third semiconductor region the concentration of n-type impurities is approximately constant.

5. A semiconductor apparatus of claim 1 , wherein within the second semiconductor region the concentration of n-type impurities is approximately constant.

6. A semiconductor apparatus of claim 1 , wherein within the drift region the concentration of n-type impurities is approximately constant.

7. A semiconductor apparatus of claim 1 , further comprising a termination region interposed between the third region and the stopper region.

8. A semiconductor apparatus comprising a semiconductor substrate, wherein:

the semiconductor substrate comprises a device region in which a vertical type IGBT is formed and a peripheral region located around the device region,

an emitter region, a first semiconductor region, a stopper region, a drift region, a collector region, and a gate electrode are formed within the device region,

the emitter region is of an n-type and exposed at an upper surface of the semiconductor substrate;

the first semiconductor region is of a p-type, a part of the first semiconductor region is exposed at the upper surface of the semiconductor substrate, the first semiconductor region is in contact with the emitter region from an underside;

the stopper region is an epitaxial layer, of the n-type, in contact with the first semiconductor region from an underside, and separated from the emitter region by the first semiconductor region;

the drift region is of n-type and located under the stopper region, the drift region has a concentration of n-type impurities lower than a concentration of the n-type impurities in the stopper region;

the collector region is of p-type and in contact with the drift region from an underside; and

the gate electrode is in contact via an insulating film with the first semiconductor region in a range separating the stopper region from the emitter region,

a second semiconductor region, a third semiconductor region, and a fourth semiconductor region are formed within the peripheral region,

the second semiconductor region is of the p-type, has a concentration of p-type impurities lower than a concentration of the p-type impurities in the first semiconductor region, is exposed at the upper surface of the semiconductor substrate, and is consecutive with the first semiconductor region directly or via another semiconductor region having the p-type,

the third semiconductor region is an epitaxial layer, of the n-type, the third semiconductor region has a concentration of the n-type impurities equal to a concentration of the n-type impurities in the stopper region, the third semiconductor region is in contact with the second semiconductor region from an underside, and a termination region interposed between the third region and the stopper region, and

the fourth semiconductor region is of the n-type, has a concentration of the n-type impurities lower than a concentration of the n-type impurities in the third semiconductor region, and is in contact with the third semiconductor region from an underside.

9. A semiconductor apparatus of claim 8 , wherein

a fifth semiconductor region is formed within the peripheral region, and

the fifth semiconductor region is of the n-type, has a concentration of the n-type impurities lower than the concentration of the n-type impurities in the third semiconductor region, is exposed at the upper surface of the semiconductor substrate, is located between the second semiconductor region and a side surface of the semiconductor substrate, and is in contact with the second semiconductor region from a lateral side.

10. A semiconductor apparatus of claim 8 , wherein the maximum value of the concentration of the p-type impurities in the second semiconductor region is higher than the maximum value of the concentration of the n-type impurities in the third semiconductor region.

11. A semiconductor apparatus of claim 8 , wherein within the third semiconductor region the concentration of n-type impurities is approximately constant.

12. A semiconductor apparatus of claim 8 , wherein within the second semiconductor region the concentration of n-type impurities is approximately constant.

13. A semiconductor apparatus of claim 8 , wherein within the drift region the concentration of n-type impurities is approximately constant.

14. A semiconductor apparatus of claim 8 , wherein the termination region is a p-type region.