Nonvolatile memory element having a tantalum oxide variable resistance layer

1. A nonvolatile memory element array comprising:

a substrate;

a plurality of first electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to a main surface of the substrate;

a plurality of second electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to the main surface of the substrate and to three-dimensionally cross the plurality of first electrode wires; and

nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires;

wherein each of the nonvolatile memory elements includes a nonvolatile memory portion and a fixed resistance portion which are provided in series to connect an associated one of the first electrode wires and an associated one of the second electrode wires;

wherein the nonvolatile memory portion includes a first electrode, a second electrode, and a variable resistance layer which is disposed between the first electrode and the second electrode, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the first electrode and the second electrode, the plurality of resistance states including a low-resistance state and a high-resistance state whose resistance value is higher than a resistance value of the low-resistance state;

wherein the variable resistance layer comprises a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx; and wherein

when a resistance value of the variable resistance layer in a state where the variable resistance layer is in the low-resistance state is RL, a resistance value of the variable resistance layer in a state where the variable resistance layer is in the high-resistance state is RH, and a resistance value of the fixed resistance portion is R 0 , R 0 satisfies RL<R 0 .

2. The nonvolatile memory element array according to claim 1 , wherein the nonvolatile memory portion and the fixed resistance portion are stacked on the same substrate.

3. The nonvolatile memory element array according to claim 1 , further comprising:

a plurality of transistors connected in series to the plurality of nonvolatile memory elements, respectively.

4. The nonvolatile memory element array according to claim 2 , further comprising:

a plurality of transistors connected in series to the plurality of nonvolatile memory elements, respectively.

5. The nonvolatile memory element array according to claim 1 , further comprising:

a plurality of rectifier elements connected in series to the plurality of nonvolatile memory elements, respectively.

6. The nonvolatile memory element array according to claim 2 , further comprising:

a plurality of rectifier elements connected in series to the plurality of nonvolatile memory elements, respectively.

7. A nonvolatile memory element array comprising:

a substrate;

a plurality of first electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to a main surface of the substrate;

a plurality of second electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to the main surface of the substrate and to three-dimensionally cross the plurality of first electrode wires;

nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires and are each configured to connect an associated one of the first electrode wires and an associated one of the second electrode wires; and

resistors respectively provided on either the plurality of first electrode wires or the plurality of second electrode wires;

wherein each of the nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer which is disposed between the first electrode and the second electrode, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the first electrode and the second electrode, the plurality of resistance states including a low-resistance state and a high-resistance state whose resistance value is higher than a resistance value of the low-resistance state;

wherein the variable resistance layer comprises a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx; and wherein

when a resistance value between the first electrode and the second electrode in a state where the variable resistance layer is in the low-resistance state is RL, a resistance value between the first electrode and the second electrode in a state where the variable resistance layer is in the high-resistance state is RH, and a resistance value of the resistor is R 0 ,

R 0 satisfies RL<R 0 .

8. The nonvolatile memory element array according to claim 7 , further comprising:

a plurality of transistors connected in series to the plurality of nonvolatile memory elements, respectively.

9. The nonvolatile memory element array according to claim 7 , further comprising:

a plurality of rectifier elements connected in series to the plurality of nonvolatile memory elements, respectively.

10. A nonvolatile memory element array comprising:

a substrate;

a plurality of first electrode wires formed on the substrate to extend in parallel with each other within a plane parallel to a main surface of the substrate;

a plurality of second electrode wires formed on the substrate to extend within a plane parallel to a main surface of the substrate and to three-dimensionally cross the plurality of first electrode wires;

a plurality of third electrode wires formed on the substrate so as to extend in parallel with each other within a plane parallel to the main surface of the substrate, to respectively correspond to the plurality of first electrode wires, and so as to three-dimensionally cross the plurality of second electrode wires;

transistors and nonvolatile memory elements, wherein each of the transistors and an associated one of the nonvolatile memory elements are provided in series to correspond to a three-dimensional cross point of an associated one of the plurality of first electrode wires and an associated one of the plurality of second electrode wires and to connect an associated one of the second electrode wires and an associated one of the third electrode wires; and

the associated one of the plurality of first electrode wires is connected to a control terminal of an associated one of the transistors, so as to correspond to the three-dimensional cross point;

wherein each of the nonvolatile memory elements includes a first electrode, a second electrode, and a variable resistance layer which is disposed between the first electrode and the second electrode, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the first electrode and the second electrode via an associated one of the transistors, the plurality of resistance states including a low-resistance state and a high-resistance state whose resistance value is higher than a resistance value of the low-resistance state;

wherein the variable resistance layer comprises a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx; and wherein

when a resistance value of the variable resistance layer in a state where the variable resistance layer is in the low-resistance state is RL, a resistance value of the variable resistance layer in a state where the variable resistance layer is in the high-resistance state is RH, and a resistance value of the transistor in an ON-state is R 0 ,

R 0 satisfies RL<R 0 .