Latching circuits for MEMS display devices
The described latching circuits can be formed using transistors of a single conductivity type. The transistors can be n-type transistors or p-type transistors. The latching circuits include at least one pre-charge transistor and at least one output terminal discharge transistor. Timing schemes are also described for operating the latching circuits. Pixel circuits and display devices that include these latching circuits are also described. The display devices are formed from an arrangement of the latching circuits.
1. An apparatus, comprising:
a plurality of MEMS devices arranged in an array; and
a control matrix comprising only n-type or only p-type transistors coupled to the plurality of MEMS devices to communicate data and drive voltages to the MEMS devices,
wherein the control matrix, for each MEMS device, comprises:
a latch configured to maintain a difference in voltage levels on a first output terminal and a second output terminal, the latch comprising:
a first pre-charge transistor and a first output terminal discharge transistor coupled to the first output terminal;
a second pre-charge transistor and a second output terminal discharge transistor coupled to the second output terminal; and
a pixel discharge transistor coupled to the first output terminal discharge transistor and the second output terminal discharge transistor;
wherein the latch is configured such that a state of the first output terminal discharge transistor is controlled based on a voltage level of the second output terminal applied to a gate of the first output terminal discharge transistor.
2. The apparatus of claim 1 , wherein the first pre-charge transistor comprises a diode-connected transistor.
3. The apparatus of claim 1 , wherein the apparatus is a display apparatus and the MEMS device comprises a shutter, and wherein the shutter is actuated based on the voltage levels on the first output terminal and the second output terminal.
4. The apparatus of claim 1 , further comprising a first latching control line coupled to the first output terminal by the first pre-charge transistor and configured to apply a first driver voltage;
wherein the first pre-charge transistor is configured to pre-charge the first output terminal from a first voltage level to a second voltage level, different from the first voltage level, based on application of the first driver voltage; and
wherein the apparatus is configured to discontinue the first driver voltage such that the first output terminal returns to the first voltage level, or maintains the first output terminal at the second voltage level, based on a voltage retained in a retention capacitor.
5. The apparatus of claim 4 , wherein an end of the retention capacitor is connected to the first latching control line, and wherein the first driver voltage acts as a bias voltage of the retention capacitor.
6. The apparatus of claim 4 , further comprising a second latching control line coupled to the second output terminal by the second pre-charge transistor and configured to apply a second driver voltage;
wherein the second pre-charge transistor is configured to pre-charge the second output terminal from the first voltage level to the second voltage level based on application of the second driver voltage; and;
wherein the apparatus is configured to discontinue the second driver voltage at a later time than the first driver voltage is discontinued such that the voltage is retained in the retention capacitor.
7. The apparatus of claim 6 , wherein the apparatus is configured to initiate the first driver voltage and the second driver voltage at a same time.
8. The apparatus of claim 1 , wherein the pixel discharge transistor controls a discharge of the first output terminal and the second output terminal through the first output terminal discharge transistor and the second output terminal discharge transistor.
9. The apparatus of claim 1 , wherein each of the first pre-charge transistor, the first output terminal discharge transistor, the second pre-charge transistor, and the second output terminal discharge transistor is configured as two transistors coupled with a common gate.
10. An apparatus, comprising:
a plurality of MEMS devices arranged in an array; and
a control matrix comprising only n-type or only p-type transistors coupled to the plurality of MEMS devices to communicate data and drive voltages to the MEMS devices,
wherein the control matrix, for each MEMS device, comprises:
a latch configured to maintain a difference in voltage levels on a first output terminal and a second output terminal, the latch comprising:
a first pre-charge transistor and a first output terminal discharge transistor coupled to the first output terminal; and
a second output terminal discharge transistor coupled to the first output terminal discharge transistor;
wherein the latch is configured such that the output of the second output terminal discharge transistor selectively controls the first output terminal discharge transistor to selectively discharge voltage stored on the first output terminal, thereby controlling a voltage level of the first output terminal.
11. The apparatus of claim 10 , wherein the first pre-charge transistor comprises a diode-connected transistor.
12. The apparatus of claim 10 , wherein the apparatus is a display apparatus and the MEMS device comprises a shutter, and wherein the shutter is actuated based on the voltage levels on the first output terminal and the second output terminal.
13. The apparatus of claim 10 , further comprising:
a first latching control line coupled to the first output terminal by the first pre-charge transistor and configured to apply a first driver voltage; and
a second latching control line coupled to the second output terminal discharge transistor and configured to apply a second driver voltage to switch the second output terminal discharge transistor;
wherein the apparatus is configured to discontinue the second driver voltage at a later time than the first driver voltage is discontinued such that the second output terminal discharge transistor controls the discharge of the first output terminal discharge transistor, thereby controlling a voltage level of the first output terminal.
14. The apparatus of claim 13 , wherein the apparatus is configured to maintain the voltage level of the first output terminal until a subsequent the first driver voltage is applied.
15. The apparatus of claim 13 , wherein the apparatus is configured to initiate the first driver voltage and the second driver voltage at a same time.
16. The apparatus of claim 13 , wherein each of the first pre-charge transistor, the first output terminal discharge transistor, and the second output terminal discharge transistor is configured as two transistors coupled with a common gate.
17. An apparatus, comprising:
a plurality of MEMS devices arranged in an array; and
a control matrix comprising only n-type or only p-type transistors coupled to the plurality of MEMS devices to communicate data and drive voltages to the MEMS devices,
wherein the control matrix, for each MEMS device, comprises:
a latch configured to maintain a difference in voltage levels on a first output terminal and a second output terminal, the latch comprising:
a first pre-charge transistor and a first output terminal discharge transistor coupled to the first output terminal; and
a first latching control line coupled to the first output terminal by the first pre-charge transistor;
wherein the first output terminal discharge transistor is coupled to an electrode of the first latching control line; and
wherein the apparatus is configured to apply to the first latching control line a first driver voltage that changes from an intermediate voltage level that has a magnitude intermediate between a first voltage level and a second voltage level, to the second level voltage, from the second voltage level to the first voltage level, and from the first voltage level to the intermediate voltage level at a time that a voltage on the first output terminal changes from the first voltage level to the second voltage level.
18. The apparatus of claim 17 , wherein the latch is configured such that applying the first driver voltage changes a voltage level of the first output terminal from the first voltage level to the second voltage level.
19. The apparatus of claim 17 , wherein the first pre-charge transistor comprises a diode-connected transistor.
20. The apparatus of claim 17 , wherein the apparatus is a display apparatus and the MEMS device comprises a shutter, and wherein the shutter is actuated based on the voltage levels on the first output terminal and the second output terminal.