Digital phase-locked loop with wide capture range, low phase noise, and reduced spurs
View Patent ↗The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.
1. A digital phase-locked loop (DPLL) for establishing and maintaining a phase relationship between an output signal and an input signal, the DPLL comprising:
a synchronizer configured to synchronize the input signal with the output signal to provide a first comparison signal;
an accumulator configured to accumulate a difference between a desired division factor and a number of edges of the output signal that occur during a cycle of the first comparison signal to provide a coarse phase error;
a multi-modulus divider (MMD) configured to reduce a frequency of the output signal, on average, by the desired division factor to provide a second comparison signal;
a time-to-digital converter (TDC) configured to detect a fine phase error based on a difference in phase between the input signal and the first comparison signal if the DPLL is in a non-locked state or detect the fine phase error between the input signal and the second comparison signal if the DPLL is in a locked state; and
a digitally controlled oscillator (DCO) configured to adjust the frequency of the output signal based on the fine phase error and, if the DPLL is in the non-locked state, the coarse phase error.
2. The DPLL of claim 1 , further comprising:
a modulator configured to control the MMD to alternately reduce the frequency of the output signal by at least a first integer division factor and a second integer division factor to provide the second comparison signal.
3. The DPLL of claim 2 , wherein the modulator is a sigma delta modulator.
4. The DPLL of claim 2 , wherein the modulator comprises:
a residual phase error accumulator configured to increment a residual phase error based on a tuning word after a cycle of the second comparison signal.
5. The DPLL of claim 4 , wherein the tuning word represents a fractional part of the desired division factor.
6. The DPLL of claim 4 , wherein the residual phase error accumulator is further configured to control the MMD to switch from reducing the frequency of the output signal by the first integer division factor to reducing the frequency of the output signal by the second integer division factor.
7. The DPLL of claim 4 , wherein the DCO is further configured to adjust the frequency of the output signal based on the residual phase error if the DPLL is in the locked state.
8. The DPLL of claim 1 , wherein the synchronizer is configured to synchronize the input signal with the output signal by registering the input signal in a storage element that is clocked by the output signal.
9. The DPLL of claim 1 , further comprising:
a counter configured to count the number of edges of the output signal that occur during the cycle of the first comparison signal.
10. The DPLL of claim 9 , wherein the edges are rising edges.
11. The DPLL of claim 9 , wherein the counter is configured to be reset by the first comparison signal.
12. A method for controlling a digital phase-locked loop (DPLL) to establish and maintain a phase relationship between an output signal and an input signal, the method comprising:
synchronizing the input signal with the output signal to provide a first comparison signal,
accumulating a difference between a desired division factor and a number of edges of the output signal that occur during a cycle of the first comparison signal to provide a coarse phase error,
reducing a frequency of the output signal, on average, by the desired division factor to provide a second comparison signal,
if the DPLL is in a non-locked state, detecting a fine phase error based on a difference in phase between the input signal and the first comparison signal and adjusting the frequency of the output signal based on the fine phase error and the coarse phase error; and
if the DPLL is in a locked state, detecting the fine phase error between the input signal and the second comparison signal and adjusting the frequency of the output signal based on the fine phase error.
13. The method of claim 12 , further comprising:
controlling a multi-modulus divider (MMD) to alternately reduce the frequency of the output signal by at least a first division factor and a second division factor to provide the second comparison signal.
14. The method of claim 13 , further comprising:
incrementing a residual phase error based on a tuning word after a cycle of the second comparison signal.
15. The method of claim 14 , wherein the tuning word represents a fractional part of the desired division factor.
16. The method of claim 14 , further comprises:
controlling the MMD to switch from reducing the frequency of the output signal by the first division factor to reducing the frequency of the output signal by the second division factor.
17. The method of claim 14 , further comprising:
if the DPLL is in the locked state, adjusting the frequency of the output signal based on the residual phase error.