Memory randomization for protection against side channel attacks

1. A method for concealing information, comprising:

performing by a computing device which is operatively coupled to a memory having first memory addresses and second memory addresses:

for each first memory address, applying a first one-to-one address relationship to such first memory address for generating a first scrambled memory address and writing data into the memory at the first scrambled memory address;

obtaining data scrambling entries from a data scrambling table;

applying a data scrambling function to the data, to an encrypted secret key and to the data scrambling entries obtained from the data scrambling table in order to generate encrypted data and decrypted data and to obtain the encrypted secret key and the decrypted secret key for storage in the memory and retrieval from the memory respectively; and

distributing the encrypted secret key and the encrypted data in the memory at respective encrypted addresses.

2. The method of claim 1 , further comprising:

accessing the memory at the encrypted addresses for respective storage and retrieval of the encrypted secret key and the encrypted data at the encrypted addresses, and retrieval of the decrypted data and the decrypted secret key.

3. The method of claim 1 , further comprising:

constructing the address scrambling table and the data scrambling table.

4. The method of claim 1 , further comprising:

generating the encrypted secret key and the decrypted secret key.

5. The method of claim 1 , further comprising:

reorganizing the memory, wherein reorganizing the memory comprises:

applying the first one-to-one address relationship a second time to read the data from the memory at the first scrambled memory address; and

writing the data into the memory at the second memory addresses by applying a second one-to-one address relationship to each such second memory address for generating a second scrambled memory address and writing data into the memory at said second scrambled memory address.

6. The method of claim 5 , further comprising:

prior to writing the data, applying a data function to prescrambled data for generating scrambled data; and

writing the scrambled data into the memory as the data.

7. The method of claim 6 , further comprising:

applying a second data function to the scrambled data to recover the prescrambled data.

8. The method of claim 6 , wherein applying the data function comprises:

applying the data function a first time to a first prescrambled data using a first data encryption key and applying the data function a second time to a second prescrambled data using a second data encryption key to generate a first scrambled data and a second scrambled data, respectively.

9. A computing device comprising:

at least one memory having first memory addresses and second memory addresses, the at least one memory storing instructions; and

a processor configured to access the at least one memory to execute the instructions stored in the at least one memory and to:

for each first memory address, apply a first one-to-one address relationship to such first memory address for generating a first scrambled memory address and writing data into the memory at the first scrambled memory address;

obtain data scrambling entries from a data scrambling table;

apply a data scrambling function to the data, to an encrypted secret key and to the data scrambling entries obtained from the data scrambling table in order to generate encrypted data and decrypted data and to obtain the encrypted secret key and the decrypted secret key for storage in the memory and retrieval from the memory respectively; and

distribute the encrypted secret key and the encrypted data in the memory at respective encrypted addresses.

10. The computing device of claim 9 , wherein the processor is further configured to:

access the memory at the encrypted addresses for respective storage and retrieval of the encrypted secret key and the encrypted data at the encrypted addresses, and retrieval of the decrypted data and the decrypted secret key.

11. The computing device of claim 9 , wherein the processor is further configured to:

construct the address scrambling table and the data scrambling table.

12. The computing device of claim 9 , wherein the processor is further configured to:

generate an encrypted secret key and a decrypted secret key.

13. The computing device of claim 9 , wherein the processor is further configured to reorganize the memory, wherein to reorganize the memory the processor is configured to:

apply the first one-to-one address relationship a second time to read the data from the memory at the first scrambled memory address; and

write the data into the memory at the second memory addresses by applying a second one-to-one address relationship to each such second memory address for generating a second scrambled memory address and writing data into the memory at the second scrambled memory address.

14. The computing device of claim 13 , wherein the processor is further configured to:

prior to writing the data, apply a data function to prescrambled data for generating scrambled data; and

write the scrambled data into the memory as the data.

15. The computing device of claim 14 , wherein the processor is further configured to:

apply a second data function to the scrambled data to recover the prescrambled data.

16. The computing device of claim 14 , wherein to apply the data function, the processor is configured to:

apply the data function a first time to a first prescrambled data using a first data encryption key and apply the data function a second time to a second prescrambled data using a second data encryption key to generate a first scrambled data and a second scrambled data, respectively.