IP Library Granted Patent US 8,383,486
Granted Patent B2
US 8,383,486 · App. 13/486,877 · Granted Feb 26, 2013

Method of manufacturing a semiconductor device including a stress film

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Quick Facts
Patent No.
US 8,383,486
App. No.
13/486,877
Granted
Feb 26, 2013
Kind
B2
Abstract

A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

Claims (12)

1. A method for fabricating a semiconductor device, comprising the steps of:

a) forming over an active region of a semiconductor substrate an internal stress film having a stress internally;

b) forming a groove reaching the active region through the internal stress film;

c) forming a gate insulating film over part of a surface of the semiconductor substrate exposed at a bottom surface of the groove;

d) filling, after the step c), the groove with a conductive film, thereby forming a gate electrode; and

e) performing, after the internal stress film has been removed, ion implantation of an impurity of a first conductive type to the active region using the gate electrode as a mask, thereby forming source/drain regions.

2. The method of claim 1 , further comprising:

before or after the step a), the step of forming over another active region of the semiconductor substrate another internal stress film having a stress in the opposite direction to that of the internal stress film internally,

wherein in the step b), another groove reaching said another active region through said another internal stress film,

wherein in the step c), another gate insulating film is formed over part of the surface of the semiconductor substrate exposed at a bottom surface of said another groove,

wherein in the step d), said another groove is filled with a conductive film, thereby forming another gate electrode, and

wherein the method further comprises the step of performing, after said another internal stress film has been removed, ion implantation of an impurity of a second conductive type to said another active region using said another gate electrode as a mask, thereby forming other source/drain regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2014
From: PANASONIC CORPORATION (FORMERLY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.)
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032152/0514 →