Monolithic semiconductor switches and method for manufacturing
A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.
1. A semiconductor device comprising:
a semiconductor die having a first and a second side opposite each other, and comprising a first n-type channel FET and a second n-type channel FET;
wherein a source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at the first side of the semiconductor die;
wherein a drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and a gate of the second n-type channel FET are electrically coupled to contact areas at the second side of the one semiconductor die;
wherein the contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other; and
wherein the first FET is a lateral FET and the second FET is a trench FET and wherein an electrical connection from the contact area of the first FET at the first side to the source of the first FET includes a conductive plug.
2. The semiconductor device of claim 1 , further comprising a Schottky diode connected in parallel to the source and the drain of the second n-type channel FET.
3. A semiconductor device comprising:
a semiconductor die having a first and a second side opposite each other, and comprising a first n-type channel FET and a second n-type channel FET;
wherein a source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at the first side of the semiconductor die;
wherein a drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and a gate of the second n-type channel FET are electrically coupled to contact areas at the second side of the one semiconductor die;
wherein the contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other; and
wherein the first n-type channel FET and the second n-type channel FET are n-type channel trench FETs, and each of the first n-type channel FET and the second n-type channel FET includes p-type body regions being part of a p-type epitaxial layer formed above an n-type semiconductor substrate of the semiconductor die, and the p-type epitaxial layer is on the n-type semiconductor substrate.
4. A semiconductor device comprising:
one semiconductor die having a first and a second side opposite each other, and comprising a first p-type channel FET and a second n-type channel FET;
wherein a drain of the first p-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at the first side of the one semiconductor die;
wherein a source of the first p-type channel FET, a gate of the first p-type channel FET, a source of the second n-type channel FET and a gate of the second n-type channel FET are electrically coupled to contact areas at the second side of the one semiconductor die; and
wherein the contact areas of the source of the first p-type channel FET, of the gate of the first p-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other;
the semiconductor device further comprising a capacitor arranged above the first side of the one semiconductor die, the capacitor being electrically coupled between the contact area of the source of the first p-type channel FET and the contact area of the source of the second n-type channel FET at the second side of the one semiconductor die; and
further comprising a capacitor arranged above the first side of the semiconductor die, the capacitor being electrically coupled between the contact area of the source of the first p-type channel FET and the contact area of the source of the second n-type channel FET at the second side of the semiconductor die.