Multilayer capacitor and method of manufacturing same
In a multilayer capacitor 1 , burned layers 17 A, 17 B are formed so as to cover all of lead conductors 12 A, 12 B drawn from inner electrodes 6 A, 6 B to end faces of a multilayer body 2 . This can keep a plating solution from infiltrating onto the inner electrodes 6 A, 6 B when forming plating layers 18 A, 18 B and prevent insulation failures from occurring. Since the burned layers 17 A, 17 B cover a part of dummy electrodes 13 C, 13 F, 13 G, 13 H, the area of the burned layers 17 A, 17 B can be suppressed. This can inhibit excessive stresses from occurring in the burned layers 17 A, 17 B and thus can prevent cracks from being generated by stresses in the burned layers 17 A, 17 B.
1. A multilayer capacitor comprising:
a multilayer body constructed by stacking a plurality of dielectric layers formed with an inner electrode;
a terminal electrode formed on a surface of the multilayer body;
a lead conductor drawn from the inner electrode to the surface of the multilayer body and connected to the terminal electrode; and
a dummy electrode separated from the inner electrode and connected to the terminal electrode;
wherein the terminal electrode has a burned layer and a plating layer each formed on the surface of the multilayer body;
wherein the burned layer covers the whole of the lead conductor and a part of the dummy electrode, in a direction along a periphery of the dielectric layer, and does not cover the rest of the dummy electrode;
wherein the plating layer covers the rest of the dummy electrode and the burned layer; and
wherein the dummy electrode is disposed on the same dielectric layer with the inner electrode corresponding thereto.
2. A multilayer capacitor according to claim 1 , wherein one side of the multilayer body is a mount surface to a substrate; and
wherein the inner electrode in the multilayer body is lopsided to the side opposite from the mount surface in the multilayer body.
3. A multilayer capacitor according to claim 2 , wherein the inner electrode is arranged substantially orthogonal to the mount surface.
4. A multilayer capacitor according to claim 1 , wherein dummy electrodes are disposed on both sides of the lead conductor interposed therebetween; and
wherein the burned layer is disposed so as to connect the dummy electrodes to each other.
5. A multilayer capacitor according to claim 2 , wherein dummy electrodes are disposed on both sides of the lead conductor interposed therebetween; and
wherein the burned layer is disposed so as to connect the dummy electrodes to each other.
6. A multilayer capacitor according to claim 3 , wherein dummy electrodes are disposed on both sides of the lead conductor interposed therebetween; and
wherein the burned layer is disposed so as to connect the dummy electrodes to each other.
7. A multilayer capacitor according to claim 4 , wherein the dummy electrodes are disposed on the same layer with the inner electrode corresponding thereto.
8. A multilayer capacitor according to claim 5 , wherein the dummy electrodes are disposed on the same layer with the inner electrode corresponding thereto.
9. A multilayer capacitor according to claim 6 , wherein the dummy electrodes are disposed on the same layer with the inner electrode corresponding thereto.
10. A multilayer capacitor according to claim 1 , wherein the dummy electrode is exposed at a region of the multilayer body excluding a corner thereof.
11. A multilayer capacitor according to claim 2 , wherein the dummy electrode is exposed at a region of the multilayer body excluding a corner thereof.
12. A multilayer capacitor according to claim 3 , wherein the dummy electrode is exposed at a region of the multilayer body excluding a corner thereof.
13. A multilayer capacitor according to claim 4 , wherein the dummy electrodes are exposed at a region of the multilayer body excluding a corner thereof.
14. A multilayer capacitor according to claim 5 , wherein the dummy electrodes are exposed at a region of the multilayer body excluding a corner thereof.
15. A multilayer capacitor according to claim 6 , wherein the dummy electrodes are exposed at a region of the multilayer body excluding a corner thereof.
16. A multilayer capacitor according to claim 1 , wherein the dummy electrode is exposed at a region of the multilayer body excluding a corner thereof.
17. A multilayer capacitor according to claim 7 , wherein the dummy electrodes are exposed at a region of the multilayer body excluding a corner thereof.
18. A multilayer capacitor according to claim 8 , wherein the dummy electrodes are exposed at a region of the multilayer body excluding a corner thereof.
19. A multilayer capacitor according to claim 9 , wherein the dummy electrodes are exposed at a region of the multilayer body excluding a corner thereof.
20. A method of manufacturing a multilayer capacitor comprising:
a multilayer body constructed by stacking a plurality of dielectric layers formed with an inner electrode;
a terminal electrode formed on a surface of the multilayer body;
a lead conductor drawn from the inner electrode to the surface of the multilayer body and connected to the terminal electrode; and
a dummy electrode separated from the inner electrode and connected to the terminal electrode, the dummy electrode being disposed on the same dielectric layer with the inner electrode corresponding thereto;
the method comprising the steps of:
forming a burned layer by burning a conductive paste applied so as to cover the whole of the lead conductor and a part of the dummy electrode, in a direction along a periphery of the dielectric layer, and not covering the rest of the dummy electrode; and
forming a plating layer on the surface of the multilayer body so as to cover the rest of the dummy electrode and the burned layer.