Embedded memory databus architecture
View Patent ↗A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors.
1. A method comprising:
charging storage cells formed at intersections of word lines and bit lines, the storage cells within a plurality of memory arrays of an embedded DRAM;
employing array select circuitry to apply first data from a selected one of a plurality of strips of bit line sense amplifiers to a plurality of data bus lines, the strips of bit line sense amplifiers electrically connected to the bit lines, and the data bus lines running in a direction parallel to the bit lines; and
transmitting the first data, via data bus read amplifiers electrically connected to the data bus lines to which the first data is applied during the employing of the array select circuitry, to outputs of the embedded DRAM without further decoding.
2. The method as claimed in claim 1 further comprising using cache registers to receive bits of the first data.
3. The method as claimed in claim 1 wherein the bit lines comprise complementary bit line pairs.
4. The method as claimed in claim 3 wherein the data bus lines comprise complementary data bus pairs.
5. The method as claimed in claim 1 wherein the array select circuitry selects the first data from a subset of sense amplifiers within the selected one of the strips of sense amplifiers to apply to the respective data bus lines.
6. The method as claimed in claim 5 wherein the subset of sense amplifier is half of the sense amplifiers in the selected one of the strips of sense amplifiers.
7. The method as claimed in claim 1 wherein the array select circuitry receives an array select signal.
8. The method as claimed in claim 1 wherein the array select circuitry also applies second data from the data bus lines to the selected one of the strips of sense amplifiers.
9. The method as claimed in claim 8 wherein the embedded DRAM includes data bus write amplifiers electrically connected to the data bus lines for providing write data from an input of the embedded DRAM to the memory arrays.
10. A method comprising:
charging storage cells formed at intersections of word lines and bit lines, the storage cells within a plurality of memory arrays of an embedded DRAM;
employing array select circuitry to apply first data from a plurality of data bus lines to a selected one of a plurality of strips of bit line sense amplifiers, the strips of bit line sense amplifiers electrically connected to the bit lines, and the data bus lines running in a direction parallel to the bit lines; and
employing data bus write amplifiers, electrically connected to the data bus lines, to apply the first data from inputs of the embedded DRAM to the data bus lines without decoding.
11. The method as claimed in claim 10 wherein the bit lines comprise complementary bit line pairs.
12. The method as claimed in claim 11 wherein the data bus lines comprise complementary data bus pairs.
13. The method as claimed in claim 10 wherein the array select circuitry applies the first data from the data bus lines to a subset of sense amplifiers within the selected one of the strips of sense amplifiers.
14. The method as claimed in claim 13 wherein the subset of sense amplifiers is half of the sense amplifiers within the selected one of the strips of sense amplifiers.
15. The method as claimed in claim 10 wherein the array select circuitry comprises FET devices controlled by array select signals.
16. The method as claimed in claim 15 wherein the FET devices are electrically coupled between sense amplifiers of the strips and the data bus lines.
17. The method as claimed in claim 10 wherein the array select circuitry carries out applying of the first data before the sense amplifiers are enabled.