IP Library Granted Patent US 8,908,384
Granted Patent B2
US 8,908,384 · App. 13/491,378 · Granted Dec 9, 2014

Motherboard substrate having no memory interconnects

Inventors: Morgan Johnson (Portland, OR); Frederick G. Weiss (Newberg, OR)
Assignee: Morgan/Weiss Technologies Inc.
G06F1/32H05K1/0243H05K2201/10378H05K2201/10159H05K1/189H05K2201/10189H01L23/32H05K1/141H05K2201/10515
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Quick Facts
Patent No.
US 8,908,384
App. No.
13/491,378
Granted
Dec 9, 2014
Kind
B2
Abstract

A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.

Claims (8)

1. A computing device, comprising:

a motherboard circuit substrate having at least a first layer of electrical interconnects, the motherboard substrate having no memory connectors;

a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects;

an interposer substrate between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects; and

at least one memory circuit on the interposer substrate, the memory circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate.

2. The computing device of claim 1 , wherein the at least one memory circuit comprises multiple memory modules.

3. The computing device of claim 2 , wherein the interposer substrate is folded to allow each memory module to have an equal path length between the memory module and the main processor.

4. The computing device of claim 1 , wherein the memory circuit comprises a solid state disk drive.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2021
From: MORGAN/WEISS TECHNOLOGIES, INC.
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 055450/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2013
From: JOHNSON, MORGAN; WEISS, FREDERICK G.
To: MORGAN/WEISS TECHNOLOGIES INC.
Reel/Frame 030770/0382 →
Continuity (3)
Continuation 13163502 · Jun 17, 2011
Provisional Application 61476501 · Apr 18, 2011
Related Publication 20120262863A1 · Oct 18, 2012