IP Library Granted Patent US 9,408,314
Granted Patent B2
US 9,408,314 · App. 13/491,388 · Granted Aug 2, 2016

Build-up printed wiring board substrate having a core layer that is part of a circuit

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Quick Facts
Patent No.
US 9,408,314
App. No.
13/491,388
Granted
Aug 2, 2016
Kind
B2
Abstract

Integrated circuits and processes for manufacturing integrated circuits are described that use printed wiring board substrates having a core layer that is part of the circuit of the printed wiring board. In a number of embodiments, the core layer is constructed from a carbon composite. In several embodiments, techniques are described for increasing the integrity of core layers in designs calling for high density clearance hole drilling. One embodiment of the invention includes a core layer that includes electrically conductive material and at least one build-up wiring portion formed on an outer surface of the core layer. In addition, the build-up portion comprises at least one micro wiring layer including a circuit that is electrically connected to the electrically conductive material in the core layer via a plated through hole.

Claims (26)

1. A printed wiring board substrate, comprising:

a core layer that includes a carbon plate;

a layer of metal that is clad by resin to one side of the carbon plate and thereby defines the outer surface of the core layer;

wherein the layer of metal includes an interior surface from which protrusions (dendrites) extend, and a plurality of the protrusions (dendrites) contact the carbon plate; and

at least one build-up wiring portion formed on the layer of metal;

wherein the build-up portion includes a dielectric layer comprising non-reinforced dielectric formed on the layer of metal; and

wherein the build-up portion comprises at least one micro wiring layer including a circuit that is electrically connected to the carbon plate in the core layer via a plated through hole.

2. The printed wiring board substrate of claim 1 , wherein the coefficient of thermal expansion of the core layer is lower than the coefficient of thermal expansion of the at least one build-up portion.

3. The printed wiring board substrate of claim 1 , wherein the core layer is configured to act as a ground plane.

4. The printed wiring board substrate of claim 1 , wherein the core layer is configured to act as a power plane.

5. The printed wiring board substrate of claim 1 , wherein the core layer is configured to act as a split power and ground plane.

6. The printed wiring board substrate of claim 1 , wherein the core layer comprises a first electrically conductive layer that is bonded to a second electrically conductive layer by a dielectric layer that electrically isolates the first layer from the second layer.

7. The printed wiring board substrate of claim 1 , wherein:

a second layer of metal is clad onto a second side of the carbon plate;

a second build-up wiring portion is formed on the second layer of metal;

a plated through hole connects a circuit on a micro wiring layer in the first build up wiring portion with a circuit on a micro wiring layer in the second build up wiring portion; and

the plated through hole is electrically isolated form the electrically conductive material in the core layer by a resin filled clearance hole.

8. The printed wiring board substrate of claim 1 , wherein the core layer has a coefficient of thermal expansion of between 0 ppm/° C. and 12 ppm/° C. in the surface spreading direction.

9. The printed wiring board substrate of claim 8 , wherein the core layer has a coefficient of thermal expansion of between 0 ppm/° C. and 9 ppm/° C. in the surface spreading direction.

10. The printed wiring board substrate of claim 1 , wherein the core layer has a thermal conductivity of between 2 W/m·K and 500 W/m·K in the surface spreading direction.

11. The printed wiring board substrate of claim 1 , wherein the core layer has a thermal conductivity of between 50 W/m·K and 1000 W/m·K in the surface spreading direction.

12. The printed wiring board substrate of claim 1 , wherein the core layer has a tensile modulus of between 5 msi and 35 msi in the surface spreading direction.

13. The printed wiring board substrate of claim 1 , wherein the core layer has a tensile modulus of between 10 msi and 40 msi in the surface spreading direction.

14. The printed wiring board substrate of claim 1 , wherein the core layer has a dielectric constant that is greater than 6.0 at 1 MHz.

15. The printed wiring board of claim 1 , wherein the core layer has a thickness that is at least 30% of the thickness of the printed wiring board substrate.

16. The printed wiring board of claim 1 , wherein the layer of metal includes an exterior surface that is planar.

Assignments (4)
SECURITY INTEREST Recorded Nov 28, 2017
From: STABLCOR TECHNOLOGY, INC.
To: KPPB LLP
Reel/Frame 044822/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: VASOYA, KALU K.
To: STABLCOR, INC.
Reel/Frame 034179/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: STABLCOR, INC.
To: DODSON, JAMES D.; CARSON, THOMAS R.; SCHNEIDER, DOUG S.
Reel/Frame 034179/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: DODSON, JAMES D.; CARSON, THOMAS R.; SCHNEIDER, DOUG S.
To: STABLCOR TECHNOLOGY, INC.
Reel/Frame 034179/0237 →