IP Library Granted Patent US 9,026,865
Granted Patent B2
US 9,026,865 · App. 13/493,023 · Granted May 5, 2015

Software handling of hardware error handling in hypervisor-based systems

Inventors: Mehdi Entezari (Collegeville, PA); Edward T. Cavanagh, Jr. (Eagleville, PA); Bryan E. Thompson (Morgantown, PA)
Assignee: Unisys Corporation
G06F9/45558G06F2009/45579G06F2009/45587
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Quick Facts
Patent No.
US 9,026,865
App. No.
13/493,023
Granted
May 5, 2015
Kind
B2
Abstract

Errors occurring on a hardware bus of a hypervisor-based system may be handled in software monitors in the hypervisor-based system. When an error occurs, guest partitions on the hypervisor-based system may be notified of the error through a monitor executing in each guest partition. Only guest partitions affected by the error may be shut down or provided other instructions for taking an action in response to the error.

Claims (48)

1. A method, comprising:

receiving, from a bus of a hypervisor-based system, an error interrupt;

identifying at least one affected guest partitions from a plurality of guest partitions executing on the hypervisor-based system; and

broadcasting the error interrupt to the affected guest partitions;

wherein when the error interrupt corresponds to a correctable error, a service partition processes the error interrupt locally, and

when the error interrupt corresponds to an uncorrectable error at a logical CPU, the method further comprises:

setting an uncorrectable error bit for each virtual CPU of the logical CPU;

determining whether the error interrupt affects any of the virtual CPUs of the logical CPU; and

signaling the guest partition corresponding to the one or more of the virtual CPUs of the existence of the error interrupt to enable the guest partition to take corrective action when the error interrupt affects one or more of the virtual CPUs of the logical CPU.

2. The method of claim 1 , in which the step of identifying the affected guest partitions comprises determining owners of a device in the hypervisor system that generated the error interrupt.

3. The method of claim 1 , in which the bus is a peripheral component interconnect express (PCI-e) bus; and the error interrupt comprises a corrupt data error interrupt.

4. The method of claim 1 , wherein the service partition processing the error interrupt comprises: taking corrective action without notifying the guest partitions and logging the error.

5. The method of claim 1 , further comprising preventing reception of further error interrupts from the bus after receiving the error interrupt.

6. The method of claim 1 , further comprising performing a corrective action after broadcasting the error interrupt and

the performing the corrective action comprises shutting down the affected guest partitions.

7. A computer program product, comprising:

a non-transitory computer readable medium comprising:

code to receive, from a bus of a hypervisor-based system, an error interrupt;

code to identify at least one affected guest partitions from a plurality of guest partitions executing on the hypervisor-based system;

code to broadcast the error interrupt to the affected guest partitions;

code to process the error interrupt locally by a service partition when the error interrupt corresponds to a correctable error; and

when the error interrupt corresponds to an uncorrectable error at a to CPU, the computer readable medium further comprises:

code to set an uncorrectable error bit for each virtual CPU of the logical CPU;

code to determine whether the error interrupt affects any of the virtual CPUs of the logical CPU; and

code to signal the guest partition corresponding to the one or more of the virtual CPUs of the existence of the error interrupt to enable the guest partition to take corrective action when the error interrupt affects one or ore of the virtual CPUs of the logical CPU.

8. The computer program product of claim 7 , in which the medium further comprises code to determine owners of a device in they hypervisor-based system that generated the error interrupt.

9. The computer program product of claim 7 , in which the bus is a peripheral component interconnect express (PCI-e) bus; and

the medium further comprises code to prevent reception of further error interrupts from the bus after receiving the error interrupt.

10. The computer program product of claim 7 , in which wherein the service partition processing the error interrupt comprises: taking corrective action without notifying the guest partitions and logging the error.

11. The computer program product of claim 10 , in which the medium further comprises code to shut down the affected guest partitions.

12. An apparatus, comprising:

a bus; and

a processor coupled to the bus, in which the processor is configured:

to receive from the bus an error interrupt;

to identify at least one affected guest partitions from a plurality of guest partitions executing on the processor;

to broadcast the error interrupt to the affected guest partitions; and

to process the error interrupt locally by a service partition when the error interrupt corresponds to a correctable error;

wherein the service partition processing the error interrupt comprises: taking corrective action without notifying the guest partitions and logging the error; and

when the error interrupt corresponds to an uncorrectable error at a logical CPU, the method further comprises:

setting an uncorrectable error bit for each virtual CPU of the logical CPU;

determining whether the error interrupt affects any of the virtual CPUs of the logical CPU; and

when the error interrupt affects one or more of the virtual CPUs of the logical CPU, signaling the guest partition corresponding to the one or more of the virtual CPUs of the existence of the error interrupt to enable the guest partition to take corrective action.

13. The apparatus of claim 12 , in which the bus is a peripheral component interconnect express (PCI-e) bus.

14. The apparatus of claim 13 , further comprising a device coupled to the bus, in which the device generates the error interrupt.

15. The apparatus of claim 14 , in which the device is a storage device and the error interrupt corresponds to a failed data storage command.

16. The apparatus of claim 14 , further comprising a root port coupled between the bus and the device.

17. The apparatus of claim 16 , in which the processor is further configured to identify affected guests by determining owners of the device generating the error interrupt.

18. The apparatus of claim 12 , in which the processor is further configured to prevent reception of further error interrupts from the bus after receiving the error interrupt.

Assignments (8)
AMENDED AND RESTATED PATENT SECURITY AGREEMENT Recorded Jun 27, 2025
From: UNISYS CORPORATION; UNISYS HOLDING CORPORATION; UNISYS NPL, INC.; UNISYS AP INVESTMENT COMPANY I
To: COMPUTERSHARE TRUST COMPANY, N.A., AS COLLATERAL TRUSTEE
Reel/Frame 071759/0527 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2020
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: UNISYS CORPORATION
Reel/Frame 054231/0496 →
SECURITY INTEREST Recorded Oct 6, 2017
From: UNISYS CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 044144/0081 →
PATENT SECURITY AGREEMENT Recorded Apr 27, 2017
From: UNISYS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 042354/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: DEUTSCHE BANK TRUST COMPANY AMERICAS, AS COLLATERAL TRUSTEE
To: UNISYS CORPORATION
Reel/Frame 030082/0545 →
RELEASE OF SECURITY INTEREST Recorded Mar 15, 2013
From: DEUTSCHE BANK TRUST COMPANY
To: UNISYS CORPORATION
Reel/Frame 030004/0619 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2012
From: ENTEZARI, MEHDI; CAVANAGH, EDWARD T., JR.; THOMPSON, BRYAN E.
To: UNISYS CORPORATION
Reel/Frame 028913/0413 →
SECURITY AGREEMENT Recorded Aug 7, 2012
From: UNISYS CORPORATION
To: DEUTSCHE BANK TRUST COMPANY AMERICAS
Reel/Frame 028736/0798 →
Continuity (1)
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