Data storage device tracking log-likelihood ratio for a decoder based on past performance
View Patent ↗A data storage device is disclosed comprising a non-volatile memory (NVM). First data is written to a first area of the NVM, and a first estimated data sequence is read from the first area of the NVM. The first estimated data sequence is first decoded, and a log-likelihood ratio (LLR) is first updated based on the first decode. Second data is written to a second area of the NVM, and a second estimated data sequence is read from the second area of the non-volatile memory. The second estimated data sequence is second decoded in response to the first updated LLR, and the LLR is second updated based on the second decode.
1. A data storage device comprising:
a non-volatile memory (NVM); and
control circuitry operable to:
write first data to a first area of the NVM;
read a first estimated data sequence comprising a first plurality of bits from the first area of the NVM;
first decode the first estimated data sequence;
first update a log-likelihood ratio (LLR) based on the first decode;
write second data to a second area of the NVM;
read a second estimated data sequence comprising a second plurality of bits from the second area of the NVM;
second decode the second estimated data sequence in response to the first updated LLR, where each updated LLR corresponds to a target bit in a plurality of consecutive bits in the second plurality of bits; and
second update the LLR based on the second decode.
2. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to second update the LLR based on a difference between the second estimated data sequence and the second decode.
3. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to:
write a test pattern to a third area of the NVM;
read a third estimated data sequence from the third area of the NVM; and
initialize the LLR based on a difference between the test pattern and the third estimated data sequence.
4. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to:
first decode the first estimated data sequence by correcting an error in the first estimated data sequence; and
first update the LLR based on the corrected error.
5. The data storage device as recited in claim 1 , wherein the consecutive bits comprises at least two consecutive bits.
6. The data storage device as recited in claim 1 , wherein the consecutive bits comprises at least three consecutive bits.
7. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to:
track a plurality of LLRs each corresponding to an operating condition; and
first update the LLR that corresponds to the operating condition when first decoding the first estimated data sequence.
8. The data storage device as recited in claim 7 , wherein the operating condition comprises a retention time of data stored in the NVM.
9. The data storage device as recited in claim 8 , wherein the operating condition comprises an ambient temperature over the retention time.
10. The data storage device as recited in claim 7 , wherein the NVM comprises a non-volatile semiconductor memory and the operating condition comprises a number of program/erase cycles of the non-volatile semiconductor memory.
11. The data storage device as recited in claim 1 , wherein the NVM comprises a non-volatile semiconductor memory.
12. The data storage device as recited in claim 1 , wherein the NVM comprises a disk of a disk drive.
13. A method of operating a data storage device comprising a non-volatile memory (NVM), the method comprising:
writing first data to a first area of the NVM;
reading a first estimated data sequence comprising a first plurality of bits from the first area of the NVM;
first decoding the first estimated data sequence;
first updating a log-likelihood ratio (LLR) based on the first decode;
writing second data to a second area of the NVM;
reading a second estimated data sequence comprising a second plurality of bits from the second area of the NVM;
second decoding the second estimated data sequence in response to the first updated LLR, where each updated LLR corresponds to a target bit in a plurality of consecutive bits in the second plurality of bits; and
second updating the LLR based on the second decode.
14. The method as recited in claim 13 , further comprising second updating the LLR based on a difference between the second estimated data sequence and the second decode.
15. The method as recited in claim 13 , further comprising:
writing a test pattern to a third area of the NVM;
reading a third estimated data sequence from the third area of the NVM; and
initializing the LLR based on a difference between the test pattern and the third estimated data sequence.
16. The method as recited in claim 13 , further comprising:
first decoding the first estimated data sequence by correcting an error in the first estimated data sequence; and
first updating the LLR based on the corrected error.
17. The method as recited in claim 13 , wherein the consecutive bits comprises at least two consecutive bits.
18. The method as recited in claim 13 , wherein the consecutive bits comprises at least three consecutive bits.
19. The method as recited in claim 13 , further comprising:
tracking a plurality of LLRs each corresponding to an operating condition; and
first updating the LLR that corresponds to the operating condition when first decoding the first estimated data sequence.
20. The method as recited in claim 19 , wherein the operating condition comprises a retention time of data stored in the NVM.
21. The method as recited in claim 20 , wherein the operating condition comprises an ambient temperature over the retention time.
22. The method as recited in claim 19 , wherein the NVM comprises a non-volatile semiconductor memory and the operating condition comprises a number of program/erase cycles of the non-volatile semiconductor memory.
23. The method as recited in claim 13 , wherein the NVM comprises a non-volatile semiconductor memory.
24. The method as recited in claim 13 , wherein the NVM comprises a disk of a disk drive.