IP Library Granted Patent US 8,487,691
Granted Patent B1
US 8,487,691 · App. 13/494,282 · Granted Jul 16, 2013

AC noise suppression from a bias signal in high voltage supply/low voltage device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,487,691
App. No.
13/494,282
Granted
Jul 16, 2013
Kind
B1
Abstract

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.

Claims (22)

1. An apparatus comprising:

a first circuit configured to generate a first control voltage and a second control voltage;

a second circuit configured to generate a bias signal in response to said first control voltage and said second control voltage; and

a third circuit configured to generate a filtered signal in response to said bias signal, wherein said filtered signal is added to said first control voltage and said second control voltage to provide alternating current (AC) noise suppression when generating said bias signal.

2. The apparatus according to claim 1 , wherein said first circuit comprises a bias circuit, said second circuit comprises a voltage divider circuit and said third circuit comprises an inverting amplifier circuit.

3. The apparatus according to claim 1 , wherein said apparatus is implemented as part of an integrated circuit (IC).

4. The apparatus according to claim 1 , wherein said first control voltage and said second control voltage comprise direct current (DC) control voltages.

5. The apparatus according to claim 1 , wherein said third circuit provides filtering of AC noise from said bias signal.

6. The apparatus according to claim 1 , wherein said third circuit comprises an inverting amplifier circuit, a resistor, and a plurality of capacitors.

7. The apparatus according to claim 6 , wherein said inverting amplifier circuit is implemented using low voltage devices operating with a high voltage supply.

8. The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits (ICs).

9. An apparatus comprising:

means for generating a first control voltage and a second control voltage;

means for generating a bias signal in response to said first control voltage and said second control voltage; and

means for generating a filtered signal in response to said bias signal, wherein said filtered signal is added to said first control voltage and said second control voltage to provide alternating current (AC) noise suppression when generating said bias signal.

10. A method for generating a bias signal, comprising the steps of:

generating a first control voltage and a second control voltage;

generating a bias signal in response to said first control voltage and said second control voltage; and

generating a filtered signal in response to said bias signal, wherein said filtered signal is added to said first control voltage and said second control voltage to provide alternating current (AC) noise suppression when generating said bias signal.

11. The method according to claim 10 , wherein said first control voltage and said second control voltage comprise direct current (DC) control voltages.

12. The method according to claim 10 , wherein said method provides filtering of AC noise from said bias signal.

13. The method according to claim 10 , wherein method is implemented using low voltage devices operating with a high voltage supply.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →