IP Library Granted Patent US 8,741,760
Granted Patent B2
US 8,741,760 · App. 13/494,728 · Granted Jun 3, 2014

Method of manufacturing semiconductor device including first conductive pattern and second conductive pattern having top surface which decreases in height

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Quick Facts
Patent No.
US 8,741,760
App. No.
13/494,728
Granted
Jun 3, 2014
Kind
B2
Abstract

A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over the plurality of first conductive patterns and the second conductive pattern, and a third conductive pattern formed over the first insulation film.

Claims (25)

1. A method of manufacturing a semiconductor device comprising:

forming a first conductive film over a semiconductor substrate;

etching the first conductive film thereby forming a plurality of first conductive patterns provided in a first direction and a second conductive pattern provided in parallel to the plurality of first conductive patterns;

covering the whole of each of the plurality of first conductive patterns and a first part of the second conductive pattern closer to the first conductive pattern with a first mask pattern, while exposing a second part of the second conductive pattern further from the first conductive pattern;

etching the second conductive pattern in a thickness direction with the first mask pattern as a mask so as not to etch the plurality of first conductive patterns and the first part of the second conductive pattern;

forming a first insulation film over the plurality of first conductive patterns and the second conductive pattern; and

forming a third conductive film over the first insulation film.

2. The method according to claim 1 , wherein an end of the first mask pattern is inclined.

3. The method according to claim 1 , wherein etching the first conductive film includes a first etching by which the second conductive pattern is isotropically etched and a second etching by which the second conductive pattern is anisotropically etched.

4. The method according to claim 1 , further comprising:

etching the third conductive film and forming a third conductive pattern extending in the first direction.

5. The method according to claim 4 , further comprising:

forming a sidewall spacer over a sidewall of the third conductive pattern.

6. The method according to claim 5 , further comprising:

forming a metal silicide layer over the third conductive pattern.

7. A method of manufacturing a semiconductor device comprising:

forming a first conductive film over a semiconductor substrate;

etching the first conductive film thereby forming a plurality of first conductive patterns provided in a first direction and a second conductive pattern provided in parallel to the plurality of first conductive patterns;

covering a part of the second conductive pattern closer to the first conductive pattern with a first mask pattern, while exposing a second part of the second conductive pattern further from the first conductive pattern;

etching the second conductive pattern in a thickness direction with the first mask pattern as a mask;

forming a first insulation film over the plurality of first conductive patterns and the second conductive pattern; and

forming a third conductive film over the first insulation film,

wherein etching the first conductive film includes a first etching by which the second conductive pattern is isotropically etched and a second etching by which the second conductive pattern is anisotropically etched.

8. The method according to claim 1 , wherein the plurality of first conductive patterns are provided so as to be adjacent each other and the first mask pattern is provided between the plurality of first conductive patterns.

9. The method according to claim 1 , wherein the first mask pattern is provided between one of the plurality of first conductive patterns and the first part of the second conductive pattern.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2012
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028771/0282 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2012
From: KOKURA, HIKARU
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 028754/0264 →