IP Library Patent Application 13495861
Patent Application
App. No. 13/495,861

SEMICONDUCTOR DEVICE

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
13/495,861
Abstract

A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Claims (32)

1 . A semiconductor device comprising:

a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and

a first substrate having an element mounting surface on which the first semiconductor chip is mounted, wherein

the first substrate includes

a plurality of first electrodes, each formed on the element mounting surface and connected to one of the element electrodes,

a plurality of first interconnects connected to the first electrodes,

a plurality of second electrodes formed on a surface opposite to the element mounting surface,

a plurality of second interconnects connected to the second electrodes,

a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects, and

a third semiconductor element,

the first substrate and the first semiconductor chip are in a rectangular planar shape,

a first side of the first substrate and a first side of the first semiconductor chip are arranged in a same direction, and

the first side of the first substrate is shorter than the first side of the first semiconductor chip.

2 . The semiconductor device of claim 1 , wherein

the first substrate has a linear expansion coefficient of 10 ppm/° C. or less.

3 . The semiconductor device of claim 1 , further comprising

a second substrate including a plurality of substrate connecting electrodes on a substrate mounting surface, wherein

the first substrate is formed above the substrate mounting surface of the second substrate, and

the second electrodes are connected to the substrate connecting electrodes via raised electrodes.

4 . The semiconductor device of claim 1 , wherein

the first semiconductor chip is flip-chip mounted.

5 . The semiconductor device of claim 1 , further comprising

a second semiconductor chip provided with a second semiconductor element including a plurality of element electrodes, wherein

the second semiconductor chip is flip-chip mounted on the element mounting surface.

6 . The semiconductor device of claim 5 , wherein

a difference between a height from the first substrate to an upper surface of the first semiconductor chip, and a height from the first substrate to an upper surface of the second semiconductor chip is 20 μm or less.

7 . The semiconductor device of claim 1 , wherein

the first electrodes are formed at smaller pitches than the second electrodes.

8 . The semiconductor device of claim 1 , wherein

a minimum interconnection width of the first interconnects is smaller than a minimum interconnection width of the second interconnects.

9 . The semiconductor device of claim 1 , wherein

the first substrate has a smaller thickness than the first semiconductor chip.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2012
From: ITOU, FUMITO; HIRANO, HIROSHIGE; OTA, YUKITOSHI
To: PANASONIC CORPORATION
Reel/Frame 028533/0034 →