Semiconductor device
Provided is a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring.
1. A semiconductor device comprising:
a first conductive type drift region;
a second conductive type body region disposed on a front surface side of the drift region;
a plurality of gate trenches disposed in a predetermined direction with an interval between one another, each of the plurality of gate trenches penetrating the body region and extending to the drift region;
a gate electrode disposed within each of the plurality of gate trenches and opposing the body region;
an insulator disposed within each of the plurality of gate trenches, each insulator being disposed between the gate electrode and a wall surface of the gate trench; and
a second conductive type diffusion region provided at a bottom portion of each of the plurality of gate trenches to surround the bottom portion, each diffusion region being surrounded by the drift region,
wherein an impurity concentration of each diffusion region is higher than that of the body region, and
wherein in the drift region, an impurity concentration of a part near a side wall surface of the gate trench in the predetermined direction is lower than that of a central part between adjacent diffusion regions.
2. The semiconductor device as in claim 1 , wherein a width of each diffusion region in the predetermined direction is longer than that of the diffusion region by which a breakdown voltage of the semiconductor device becomes maximum, and is shorter than a width of the diffusion region by which adjacent diffusion regions contact each other.
3. The semiconductor device as in claim 2 , further comprising a blocking region protruding from the side wall surface of the gate trench in the predetermined direction to the drift region, and blocking a carrier flow from the diffusion region toward the gate electrode.