MOS transistor having combined-source structure with low power consumption and method for fabricating the same
The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.
1. A method for fabricating a MOS transistor having a combined-source structure with low power consumption, comprising the following steps:
1) defining an active region over a semiconductor substrate by a shallow isolation;
2) growing a gate dielectric layer;
3) depositing a gate electrode layer, and then forming a main gate pattern and a extending gate pattern by photolithographing and etching the gate electrode layer;
4) performing photolithographing to form a doped source region, and performing an ion implantation by using a photoresist and the gate as a mask to form a highly-doped source region;
5) performing photolithographing to form a doped drain region, and performing an ion implantation by using a photoresist and the gate as a mask to form a highly-doped drain region; and performing a rapid high temperature annealing to activate the doped impurities;
6) performing photolithographing to form a metal region in the source, sputtering a metal layer, and performing a low temperature annealing to form a compound made of the metal and the semiconductor; and then removing the unreacted metal to form a Schottky source region; and
7) performing conventional CMOS subsequent processes, comprising depositing a passivation layer, opening a contact hole, and a metallization, to form the MOS transistor.
2. The method according to claim 1 , wherein, in the step 1), the semiconductor substrate material is selected from Si, Ge, SiGe, GaAs, or other binary or ternary compound semiconductor from II-VI, III-V and IV-IV group, silicon-on-insulator, or germanium-on-insulator.
3. The method according to claim 1 , wherein, in the step 2), a material of the gate dielectric layer is selected from silicon oxide, hafnium oxide, hafnium nitride, and etc.
4. The method according to claim 1 , wherein, in the step 2), a method for growing the gate dielectric layer is selected from one of the following methods: a conventional thermal oxidation, a nitrided thermal oxidation, a chemical vapor deposition, and a physical vapor deposition.
5. The method according to claim 1 , wherein, in the step 3), a material of the gate electrode layer is selected from doped polysilicon, cobalt, nickel, and other metal or metallic silicide.
6. The method according to claim 1 , wherein, in the step 6), the metal material is selected from Pt, Er, Co, Ni, and other metal which reacts with the substrate semiconductor material and forms a compound by annealing.