IP Library Granted Patent US 8,574,957
Granted Patent B2
US 8,574,957 · App. 13/502,769 · Granted Nov 5, 2013

Method for manufacturing nonvolatile semiconductor memory element

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Quick Facts
Patent No.
US 8,574,957
App. No.
13/502,769
Granted
Nov 5, 2013
Kind
B2
Abstract

An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film.

Claims (22)

1. A method for manufacturing a nonvolatile semiconductor memory element, comprising:

forming a contact plug above a substrate;

depositing a first conductive film so that the contact plug is covered therewith;

depositing, on the first conductive film, a variable resistance film including multiple layers having different oxygen content percentages;

depositing a second conductive film on the variable resistance film;

forming a top electrode by patterning the second conductive film;

forming a variable resistance layer by patterning the variable resistance film; and

forming a bottom electrode connected to the contact plug, by patterning the first conductive film,

said method further comprising oxidizing to insulate an end portion of the variable resistance layer or a portion of the variable resistance film which is to be the end portion of the variable resistance layer, at least prior to forming the bottom electrode.

2. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 1 ,

wherein the oxidizing is oxidizing to insulate the end portion of the variable resistance layer after forming the variable resistance layer.

3. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 1 ,

wherein the oxidizing is oxidizing to insulate the portion of the variable resistance film after forming the top electrode and before forming the variable resistance layer.

4. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 3 ,

wherein the variable resistance layer includes a tantalum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.

5. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 1 , further comprising forming, above the top electrode, an anti-stress layer having a higher compressive stress than the top electrode.

6. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 5 ,

wherein the variable resistance layer includes a tantalum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.

7. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 1 ,

wherein the variable resistance layer includes a tantalum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.

8. The method for manufacturing the nonvolatile semiconductor memory element, according to claim 2 ,

wherein the variable resistance layer includes a tantalum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2012
From: MIKAWA, TAKUMI; HAYAKAWA, YUKIO; NINOMIYA, TAKEKI; KAWASHIMA, YOSHIO
To: PANASONIC CORPORATION
Reel/Frame 028680/0092 →