OTP memory cell having low current leakage
A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116 , are formed in twin wells 102 & 104 . The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104 . The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.
1. A memory device comprising:
a first well of a first type;
a second well of a second type formed adjacent to the first well;
an anti-fuse device formed over the second well with a first polysilicon gate doped to be the second type;
an isolation region in the second well and adjacent to the first polysilicon gate;
and,
an access device formed over the first well with a second polysilicon gate for electrically coupling the anti-fuse device to a bitline contact; and
a diffusion region in the first well and electrically connected to the bitline contact.
2. The memory device of claim 1 , wherein the anti-fuse device has a first gate oxide and the access device has a second gate oxide, the second gate oxide being thicker than the first gate oxide.
3. The memory device of claim 2 , further including a core transistor device formed in a third well identical to the second well.
4. The memory device of claim 3 , wherein the core transistor has a gate oxide substantially identical in thickness to the first gate oxide.
5. The memory device of claim 2 , further including an input/output transistor device formed in a third well identical to the first well.
6. The memory device of claim 5 , wherein the input/output transistor device has a gate oxide substantially identical in thickness to the second gate oxide.
7. The memory device of claim 2 , wherein the anti-fuse device and the access device are formed together as a split-channel anti-fuse memory cell having a variable thickness gate oxide.
8. The memory device of claim 4 , wherein the access device is electrically coupled to the anti-fuse device through a diffusion region.
9. The memory device of claim 8 , wherein the diffusion region includes a lightly doped drain (LDD) region extending towards the first polysilicon gate and the second polysilicon gate.
10. The memory device of claim 8 , wherein the anti-fuse device includes a split-channel anti-fuse memory cell having a variable thickness gate oxide formed on the second well.
11. The memory device of claim 10 , wherein the split-channel anti-fuse memory cell includes an access device portion and an anti-fuse device portion.
12. The memory device of claim 11 , wherein the access device portion has a third gate oxide, the third gate oxide being thicker than the first gate oxide.
13. The memory device of claim 12 , wherein the second gate oxide and the third gate oxide are substantially the same thickness.
14. The memory device of claim 8 , wherein the first gate oxide of the anti-fuse device has a uniform thickness underneath an entire length of the first polysilicon gate.
15. The memory device of claim 14 , wherein the diffusion region includes a lightly doped drain (LDD) region extending towards the second polysilicon gate.
16. The memory device of claim 15 , wherein the diffusion region omits an LDD region extending towards the first polysilicon gate.
17. The memory device of claim 16 , wherein the anti-fuse device includes a first sidewall spacer formed adjacent to the first polysilicon gate, and the access device includes a second sidewall spacer formed adjacent to the second polysilicon gate, the first sidewall spacer being thicker than the second sidewall spacer.
18. A memory array comprising,
anti-fuse devices formed over wells of a first type;
isolation regions in the wells of the first type adjacent to gate oxides of the anti-fuse devices for isolating the anti-fuse devices from other devices;
access devices formed over wells of a second type opposite to the first type for electrically coupling the anti-fuse devices to corresponding bitlines, wherein the wells of a second type are formed adjacent to the wells of the first type; and,
diffusion regions in the wells of the second type and electrically connected to the bitlines.
19. The memory array of claim 18 , wherein the anti-fuse devices includes polysilicon gates doped to be the first type.
20. The memory array of claim 18 , wherein each of the anti-fuse devices and the access devices are formed as a single transistor anti-fuse memory cell having a variable thickness gate oxide, where the anti-fuse device has a first gate oxide thickness and the access device has a second gate oxide thickness greater than the first gate oxide thickness.