CMOS device for reducing radiation-induced charge collection and method for fabricating the same
A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.
1. A method for fabricating a CMOS device for reducing a radiation-induced charge collection, comprising:
1) providing a semiconductor substrate;
2) thermally growing a silicon dioxide layer on the substrate as a buffer layer and depositing a silicon nitride layer; defining a field region by photolithography technology and etching the silicon nitride layer by reactive ion etching; performing an implantation for the field region; depositing a silicon dioxide layer and a barrier layer and planarizing a resultant surface by chemical-mechanical polishing to form a device isolation region;
3) performing a cleaning; after the cleaning, growing a gate dielectric layer and depositing a gate electrode layer; defining a gate pattern by photolithography technology, etching the gate electrode layer and the gate dielectric layer outside the pattern to form a gate region; and performing an implantation for a LDD region to form the LDD region;
4) depositing a silicon oxide layer or a silicon nitride layer and anisotropically etching the silicon oxide layer or the silicon nitride layer to form a gate sidewall;
5) depositing a barrier layer and anisotropically etching the barrier layer to form a barrier layer sidewall;
6) performing a heavily-doped ion implantation to form a charge collection-suppressed region;
7) etching the barrier layer sidewall, performing implantation for a source region and a drain region with impurities, wherein the source region and the drain region have implantation depths less than that of the heavily doped charge collection-suppressed region and have doping types opposite to that of the charge collection-suppressed region, and activating the impurities by rapid annealing technology to form the source region and the drain region.
2. The method according to claim 1 , wherein the gate dielectric layer in the step 3) is silicon dioxide or a high-K material.
3. The method according to claim 1 , wherein the gate electrode layer in the step 3) is polysilicon or a metal.
4. The method according to claim 1 , wherein the barrier layer in the step 5) is silicon dioxide or silicon nitride.