GRAPHICS VERTEX PROCESSING DEVICE, IMAGE PROCESSING DEVICE, GRAPHICS VERTEX PROCESSING METHOD AND RECORDING MEDIUM
A microcode RAM obtains, from a host computer, a microcode including an instruction sequence and a composite instruction sequence coupling a plurality of instruction sequences together to sort the micro instructions and to process the plurality of instruction sequences in a parallel manner and stores the obtained microcode. An address table obtains the header address of the microcode from the host computer, and stores the obtained header address. An FIFO buffer stores information on a vertex subjected to an arithmetic processing and an instruction sequence index for identifying the content of the arithmetic processing for the information on the vertex. An instruction determination unit selects the microcode based on the successive instruction sequence indexes obtained from the FIFO buffer. An arithmetic processing execution unit executes the arithmetic processing on the information on the vertex based on the microcode selected by the instruction determination unit.
1 . A graphics vertex processing device comprising:
a microcode storing unit that stores a microcode including an instruction sequence and a composite instruction sequence, the composite instruction sequence containing a plurality of instruction sequences coupled together so as to sort micro instructions and to process the plurality of instruction sequences in a parallel manner;
a buffer that stores information on a vertex subjected to an arithmetic processing and an instruction sequence index for identifying a content of the arithmetic processing for the information on the vertex;
instruction selection unit that selects a microcode corresponding to the number of successive instruction sequence indexes from microcodes stored in the microcode storing unit based on one or equal to or greater than two successive instruction sequence indexes stored in the buffer; and
an arithmetic processing unit that executes an arithmetic processing on the information on the vertex based on the selected microcode by the instruction selection unit.
2 . The graphics vertex processing device according to claim 1 , further comprising an address table containing an index for identifying an instruction sequence included in each microcode, and a code for identifying the microcode stored in the microcode storing unit,
wherein the instruction selection means unit refers to the address table to select the microcode based on one or equal to or greater than two successive instruction sequence indexes stored in the buffer.
3 . The graphics vertex processing device according to claim 2 , wherein
the address table contains, for each index of the microcode, a flag for distinguishing a microcode stored in the microcode storing unit and a microcode not stored in the microcode storing unit, and
the instruction selection unit refers to the flag in the address table to select the microcode.
4 . An image processing device comprising:
the graphics vertex processing device according to claim 1 ; and
a computer which generates a microcode containing an instruction sequence and a composite instruction sequence, the composite instruction sequence containing a plurality of instruction sequences coupled together so as to sort micro instructions and to process the plurality of instruction sequences in a parallel manner, supplies the generated microcode to the graphics vertex processing device, generates information on a vertex subjected to an arithmetic processing and an instruction sequence index for identifying a content of the arithmetic processing for the information on the vertex, and supplies the generated information and instruction sequence index to the graphics vertex processing device.
5 . A graphics vertex processing method comprising:
a step of storing, in a microcode storing unit, a microcode including an instruction sequence and a composite instruction sequence, the composite instruction sequence containing a plurality of instruction sequences coupled together so as to sort micro instructions and to process the plurality of instruction sequences in a parallel manner;
a step of obtaining information on a vertex subjected to an arithmetic processing and an instruction sequence index for identifying a content of the arithmetic processing for the information on the vertex and storing the obtained information and instruction sequence index in a buffer;
an instruction selection step of selecting a microcode corresponding to the number of successive instruction sequence indexes from microcodes stored in the microcode storing unit based on one or equal to or greater than two successive instruction sequence indexes stored in the buffer; and
an arithmetic processing step of executing an arithmetic processing on the information on the vertex based on the microcode selected in the instruction selection step.
6 . The graphics vertex processing method according to claim 5 , wherein the instruction selection step
refers to an address table containing an index for identifying an instruction sequence included in each microcode, and a code for identifying the microcode stored in the microcode storing unit, and
selects the microcode based on one or equal to or greater than two successive instruction sequence indexes stored in the buffer.
7 . The graphics vertex processing method according to claim 6 , wherein
the address table contains, for each index of the microcode, a flag for distinguishing a microcode stored in the microcode storing unit and a microcode not stored in the microcode storing unit, and
the instruction selection step refers to the flag in the address table to select the microcode.
8 . The graphics vertex processing method according to claim 5 , further comprising:
a step of generating the microcode; and
a step of generating the information on the vertex subjected to the arithmetic processing and the instruction sequence index for identifying the content of the arithmetic processing for the information on the vertex.
9 . A computer-readable recording medium storing a program that allows a computer to function as:
storing unit that stores a microcode including an instruction sequence and a composite instruction sequence with a plurality of instruction sequences coupled together so as to sort micro instructions and to process the plurality of instruction sequences in a parallel manner;
obtaining unit that obtains information on a vertex subjected to an arithmetic processing and an instruction sequence index for identifying a content of the arithmetic processing for the information on the vertex and storing the obtained information and instruction sequence index in a buffer;
instruction selection unit that selects a microcode corresponding to the number of successive instruction sequence indexes from microcodes stored in the storing unit based on one or equal to or greater than two successive instruction sequence indexes stored in the buffer; and
arithmetic processing unit that executes an arithmetic processing on the information on the vertex based on the microcode selected in the instruction selection step.